Negative Bias Temperature Instability-Aware Instruction Scheduling: A Cross-Layer Approach

摘要

VLSI systems fabricated at nanoscale technology nodes are more vulnerable to various aging effects, such as transistor aging due to Negative Bias Temperature Instability (NBTI). The result is a transistor threshold voltage shift over time, which increases device delays causing more timing failures in the field and eventually faster wearout of the system. In this paper we present a cross-layer approach that combines knowledge from circuit-, microarchitecture- and application-level to efficiently mitigate transistor aging. Our proposed technique uses a novel aging-aware instruction scheduling with specialized functional units to alleviate the impact of NBTI-induced wearout. To achieve this, all instructions are classified depending on their worst-case (circuit-level) delay and their occurrence frequency (at application-level) into critical and non-critical instructions. During the execution, each of these classes uses its own (specialized) functional unit(s). By that means it is possible to increase the idle ratio of the units executing the critical instructions, which can be used to efficiently extend lifetime compared to a balanced scheduling policy. Our results show that MTTF of the functional units can be significantly extended. At the same time, performance is not impacted and the additional area as well as power costs are minor.