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首页> 外文期刊>IEEE Journal of Solid-State Circuits >Effects of substrate resistances on LNA performance and a bondpad structure for reducing the effects in a silicon bipolar technology
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Effects of substrate resistances on LNA performance and a bondpad structure for reducing the effects in a silicon bipolar technology

机译:衬底电阻对LNA性能的影响以及用于减小硅双极技术影响的焊盘结构

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摘要

The effects of substrate resistances on the performance of 5.8-GHz low-noise amplifiers (LNAs) have been evaluated through a combination of experimental and simulation studies. The substrate resistive network for the LNA has been constructed by fabricating and measuring a test structure. The substrate resistances can be significantly affected by the die area and thickness, which raises a serious concern for on-wafer testing and optimization of circuits using the test results. The substrate resistances reduce the simulated gain by more than 10 dB and increase the noise figure by 2.7 dB. The simulation study has shown that the dominant substrate resistances are those associated with the bondpads. To reduce the effects of the substrate resistances, a ground-shielded bondpad structure, which consists of a Metal 2 pad and an n/sup +/ plug grounded shield separated by a composite oxide layer, has been developed. It reduces the resistance to ground to almost zero by conducting the signal away from the substrate to ground through the low-resistivity n/sup +/ plug layer. The pad structure in addition improves the interpad isolation by as much as 35 dB. However, to harness this isolation improvement, the inductance between the IC and PC board ground should be made small by using a low ground inductance package. Using this ground-shielded bondpad, the measured gain and noise figure of a 4.5-GHz tuned amplifier were improved by 10 and 2 dB, respectively, over the same circuit implemented using the conventional bondpad.
机译:通过实验和仿真研究相结合,评估了基板电阻对5.8 GHz低噪声放大器(LNA)性能的影响。 LNA的衬底电阻网络是通过制造和测量测试结构而构建的。芯片的面积和厚度会严重影响衬底的电阻,这严重影响了晶圆上测试和使用测试结果进行电路优化。基板电阻会将模拟增益降低10 dB以上,并使噪声系数增加2.7 dB。仿真研究表明,主要的衬底电阻是与焊盘相连的电阻。为了减少衬底电阻的影响,已经开发了一种接地屏蔽的焊盘结构,该结构由金属2焊盘和被复合氧化物层隔开的n / sup + /插头接地屏蔽层组成。通过将信号通过低电阻率n / sup + /插塞层从基板传到地面,可将对地的电阻降低到几乎为零。焊盘结构还使焊盘间隔离度提高了35 dB。但是,为了利用这种隔离改进,应使用低接地电感封装来减小IC和PC板接地之间的电感。使用该接地屏蔽焊盘,与使用常规焊盘实现的相同电路相比,4.5 GHz调谐放大器的测量增益和噪声系数分别提高了10 dB和2 dB。

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