Split-level precharge differential logic: a new type of high-speedcharge-recycling differential logic

摘要

In this paper, a new charge-recycling differential logic namednsplit-level precharge differential logic (SPDL) is presented. It employsna new push-pull type output driver which is simple and separated fromnthe NMOS logic tree. Therefore, it can improve energy efficiency,ndriving capability, and reliability compared with the previousndifferential logic structures which use cross-coupled inverters as thenoutput driver. To verify the reliability and the applicability of thenproposed SPDL in VLSI systems, an 8-bit full adder is fabricated in an0.6-Μm CMOS technology. Experimental results show that thenperformance of the SPDL is about two times as good as that of thenprevious half-rail differential logic (HRDL) in terms of power-delaynproduct. Moreover, the SPDL has stable operation under mismatch ornparameter variation