12-bit low-power fully differential switched capacitornoncalibrating successive approximation ADC with 1 MS/s

摘要

Based on a conventional successive approximation ADC architecture,na new and faster solution is presented. The input structure of the newnsolution consists of transmission gates and capacitors only and there isnno need for any active element. A switching circuit is implemented tonallow a wider input voltage range of the ADC. Together with a self-timedncomparator, the power consumption is noticeably reduced while at thensame time the sampling rate is doubled. Smaller input and referencencapacitances reduce the requirements on the input and reference sources,nrespectively. Additionally, a widely clock-duty-cycle-independentncontrol logic improves the applicability of the converter cell,nespecially for systems on chip. Results of measurements confirm thentheoretical improvements