Two-dimensional DC and small-signal analysis of gate-to-source scaling effects in SiC-based high-power field-effect transistors have been performed in this paper. The simulation results show that a downscaling of gate-to-source distance can improve device perfor- mance, i.e. enhancing drain current, transconductance, and maximum oscillation frequency. This is associated with the peculiar dynamic of electrons in SiC MESFETs, which lead to a linear velocity regime in the source access region. The variations of gate-to-source capacitance, gate-to-drain capacitance, and cut-off frequency with respect to the change in gate-to-source length have also been studied in detail.
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