Energy-aware loops mapping on multi-vdd CGRAs without performance degradation

摘要

Coarse Grained Reconfigurable Architectures (C-GRAs) have been paid an increasing attention due to their inherent advantages of high performance and energy efficiency. As we know, multi-Vdd technique is popularly used to reduce energy consumption, and modulo scheduling is one of widely-used pipeline techniques to improve performance. To achieve both high performance and energy-efficiency simultaneously, this paper proposes an energy-aware mapping algorithm integrating multi-Vdd assignment into the scheduling and mapping procedures of loop applications. Also, an energy-aware FDS (eFDS) algorithm and a rapid MCC searching method based on compatibility concept are successfully adopted to solve the bi-objective optimization problem. The experimental results show that the proposed approach brings 18.7% energy reduction and 1.44X energy-efficiency improvement while keeping optimized performance.