Automatic generation of test vectors for sequential circuits

摘要

The disclosure concerns the automatic generation of test vectors for a sequential circuit which is expressible as a finite state machine having a combinatorial part and sequential elements. A functional generation of test vectors is performed using a high level functional specification of the finite state machine. Fault simulation may be used to provide a list of possible faults not covered by the vectors generated functionally. A structural generation performed on the combinatorial part in respect of the listed faults provides test vectors for all the remaining faults except those which are due to redundancy in the circuit. The high level specification can be modified for the purpose of test generation without modifying its functionality to add transitions corresponding to the structurally generated vectors and the functional generation may be performed on the modified specification to provided a final set of test vectors. The disclosed method enables the automatic generation of text vectors without any design modification and providing a high fault coverage with fewer design constraints.