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Dynamic and differential CMOS logic with signal-independent power consumption to withstand differential power analysis
Dynamic and differential CMOS logic with signal-independent power consumption to withstand differential power analysis
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机译:动态和差分CMOS逻辑,具有与信号无关的功耗,可承受差分功率分析
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摘要
A dynamic and differential CMOS logic style is disclosed in which a gate uses a fixed amount of energy per evaluation event. The gate switches its output at every event and loads a constant capacitance. The logic style is a Dynamic and Differential Logic (DDL) style. The DDL style logic typically has one charging event per clock cycle and the charging event does not depend on the input signals. The differential feature masks the input value because a precharged output nodes is discharged during the evaluation phase. The dynamic feature breaks the input sequence: the discharged node is charged during the subsequent precharge phase.
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