首页> 外国专利> A COMPLEX VALUED DELTA SIGMA PHASE LOCKED LOOP DEMODULATOR

A COMPLEX VALUED DELTA SIGMA PHASE LOCKED LOOP DEMODULATOR

机译:复数值DELTA SIGMA锁相环解调器

摘要

The demodulator (10) is a multiple stage demodulator. The first stage is a conversion stage (20) which converts an incoming signal (80) into a first complex representation (60/70). The second stage is a direct digital synthesizer (DDS) / mixer (30) which synthesizes a signal to be mixed with the first complex signal (60/70) and performs the mixing operation to produce a second complex output (120). This second complex signal (120) is controlled by a bitstream (100) fed back from the third stage - a phase quantizer stage (40). The bitstream (100) represents the quantized phase difference between the synthesized signal and the first complex signal (60/70). The DDS/mixer stage (30) then measures the synthesized signal for any phase difference from the incoming signal (80) through the feedback inherent to a PLL, the bitstream (100) thus provides an output that gives the frequency of the desired signal. As a side benefit, the real component (110) of the second complex signal (120), provides an amplitude estimate of the desired signal.
机译:解调器(10)是多级解调器。第一级是转换级(20),其将输入信号(80)转换成第一复数表示(60/70)。第二阶段是直接数字合成器(DDS)/混频器(30),其将要与第一复合信号(60/70)混合的信号进行合成并执行混合操作以产生第二复合输出(120)。该第二复合信号(120)由从第三级-相位量化器级(40)反馈的比特流(100)控制。比特流(100)表示合成信号与第一复信号(60/70)之间的量化相位差。然后,DDS /混频器级(30)通过PLL固有的反馈来测量来自输入信号(80)的任何相位差的合成信号,比特流(100)因此提供给出期望信号频率的输出。作为附带好处,第二复信号(120)的实分量(110)提供了所需信号的幅度估计。

著录项

  • 公开/公告号IN248688B

    专利类型

  • 公开/公告日2011-08-12

    原文格式PDF

  • 申请/专利权人

    申请/专利号IN401/DELNP/2003

  • 发明设计人 RILEY TOM;

    申请日2003-03-17

  • 分类号H03D3/08;

  • 国家 IN

  • 入库时间 2022-08-21 18:05:34

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