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COMPLEX VALUED DELTA SIGMA PHASE LOCKED LOOP DEMODULATOR

机译:复数值DELTA SIGMA锁相环解调器

摘要

The demodulator is a multiple stage demodulator. The first stage is aconversion stage which converts an incoming signal into a first complexrepresentation. The second stage is a direct digital synthesizer (DDS)/mixerwhich synthesizes a signal to be mixed with the first complex signal andperforms the mixing operation to produce a second complex output. This secondcomplex signal is controlled by a bitstream fed back from the third stage - aphase quantizer stage. The bitstream represents the quantized phase differencebetween the synthesized signal and the first complex signal. The DDS/mixerstage then measures the synthesized signal for any phase difference from theincoming signal through the feedback inherent to a PLL, the bitstream thusprovides an output that gives the frequency of the desired signal. As a sidebenefit, the real component of the second complex signal, provides anamplitude estimate of the desired signal.
机译:解调器是多级解调器。第一阶段是转换级,将输入信号转换为第一复数表示。第二阶段是直接数字合成器(DDS)/混频器合成要与第一个复数信号混合的信号,然后执行混合操作以产生第二个复数输出。这第二复杂信号由从第三级反馈的比特流控制-相位量化器阶段。比特流代表量化的相位差在合成信号和第一复数信号之间。 DDS /混音器阶段然后测量合成信号中与通过PLL固有的反馈输入信号,因此比特流提供一个输出,该输出给出所需信号的频率。作为一面好处,第二个复信号的实分量,提供了所需信号的幅度估计。

著录项

  • 公开/公告号CA2422794C

    专利类型

  • 公开/公告日2011-08-23

    原文格式PDF

  • 申请/专利权人 RILEY TOM;

    申请/专利号CA20012422794

  • 发明设计人 RILEY TOM;

    申请日2001-09-19

  • 分类号H03D3/00;H03D7/16;H04L27/233;

  • 国家 CA

  • 入库时间 2022-08-21 18:02:28

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