GENERATION OF MODULE AND SYSTEM-LEVEL WAVEFORM SIGNATURES TO VERIFY, REGRESSION TEST AND DEBUG SOC FUNCTIONALITY

摘要

A method of detecting a fault in a circuit design undergoing emulation, includes in part, computing N signatures of a corresponding reference circuit design during each of the N cycles, computing N signatures of the circuit design undergoing emulation during each of the N cycles, comparing, for each of the N cycles, the signature of the reference circuit design to the signature of the circuit design undergoing emulation, and detecting whether a mismatch exists between the reference circuit design signature and the signature of the circuit design undergoing emulation during each of the N cycles. The method further includes comparing the signatures of the submodules of the reference circuit design to the signatures of the corresponding submodules of the circuit design undergoing emulation to enable root causing submodule functional failures. Optionally, each signature may computed by performing a logic function on a multitude of output signals of the circuit design.