A 16 nm Robust DG-FinFET Based 10T Static Random-Access Memory Cell Design for Ultra-Low Power Memory Design

摘要

In today's world, SRAM goes into the development stage, to withstand higher process variation and support ultra-low power application. Memories occupy more than 80 percent of the area in today's system on chip and the trends continue to increases in coming next years. The bulk MOSFETfaces various challenges which lead to increased leakage current at lower technology nodes. Below 45 nm technology, FinFET is the most promising alternative to bulk CMOS because of reduced short channel effect and higher stability. The proposed SRAM cell is designed using MOSFET, FinFET at16 nm technology node and its performance parameters such as power, delay, Power Delay Product (PDP), leakage current and Static Noise Margin (SNM) are compared with conventional 6T SRAM cell.