High Speed Low Power Ping Pong Buffering Based Network Interface for Network on Chip

摘要

Connecting different Intellectual Property (IP) cores with the Network on Chip (NoC) router using a Network Interface (NI) is a challenging task due to its asynchronous nature and data width. In this paper, a generic high-speed NI for NoC using Ping Pong Buffers is proposed, in order to ensure low power and seamless high throughput between the router and processing IP core. The proposed scheme uses simple control logic to handle the read and write operations simultaneously from/to the memory modules and disables the unused memory banks as per the data flow required to achieve low power. This proposed method is analyzed with the existing Asynchronous First in First Out (FIFO) based NIs with different encoding schemes like One-Hot encoding and Johnson encoding. The NI is implemented using the asynchronous FIFOs and ping pong - double buffering scheme in Altera Stratix III FPGA. The synthesis results show that the proposed architecture enhances the speed of NI by 30% when memory depth is 8 and enhances speed by 11% when memory depth is 256. The power reduction is 12% and 5% when the memory size is 8 and 30% and 17% when the memory size is 256 for the transaction from PE to Router banks and Router to PE banks respectively.