A Novel Design of Seven Segment Decoder Using Cyclic Combinational Technique

摘要

A "Cyclic Combinational Circuit" is defined as the circuit, the output of which depends on present inputs only, but simultaneously contains one or more topological feedback paths. Often, deliberate incorporation of such cycles/feedbacks in conventional combinational circuit eventually results in less number of transistor counts leading to improved speed and power performance. In the present work, well known Seven Segment Decoder (SSD) circuit was investigated as a test circuit with a cyclic representation with an aim to optimize area, power and delay. The design was carried out using standard CADENCE simulator with 180 nm technologies and the SSD using cyclic combinational technique was found to offer about 44%, 45% and 34% improvement in area, power and speed respectively, compared to its conventional counterparts.