Switched-Capacitor Based Buck Converter Design Using Current Limiter

摘要

A CMOS switched-capacitor DC-DC step-down converter topology for embedded application is proposed. The converter can be designed with integrable flying capacitors, small output ripple and good power efficiency but by increasing switching frequency. The main theme of our proposed topology is to limit the in-rush current from the supply during charge refreshing mode of the flying capacitance and hence, improves power efficiency and reduces output ripple. We have used voltage controlled current source as a limiter where control voltage is used to get a good load regulation at a specific output voltage. We have also proposed an equivalent macro-model of this type of current limiter based switched-capacitor converter which would help to get a better essence of the closed loop fast scale stability of the system and would reveal clearly trade-offs among load current, flying capacitance and clock frequency. The proposed buck converter is designed in 0.18 μ technology with thick gate devices. For a load current of 8 mA the achieved power efficiency is 72.7% and the output ripple is 27 mV at 1.35 V output regulated voltage. The flying capacitors in the converter are 2 × 108 pF and the load capacitor is 125 pF.