Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels

摘要

This paper presents an adaptive LDPC decoder design that dynamically adjusts performance to optimize gain/power for additive white Gaussian noise (AWGN) channels. The proposed decoding scheme provides constant-time decoding and thus facilitates real-time applications where guaranteed data rate is required. It analyzes each received data frame to estimate the minimum number of necessary iterations necessary for the data frame convergence. The results are then used to dynamically schedule decoder frequency and to select/switch to corresponding minimum voltage level. It differs from recent publications on speculative LDPC decoding for block-fading channels. This approach addresses the more difficult problem of decoding requirement prediction for data frames in AWGN channels. It is also directly applicable for fading channels. A decoder architecture utilizing offset min-sum layered decoding algorithm is presented. Up to 30% saving in decoding energy consumption is achieved with negligible coding performance degradation.