Defect Tolerant Voter Designs Based on Transistor Redundancy

摘要

This paper addresses defect-tolerant voter designs, using Transistor Redundancy (TR). Six to seven redundant transistors are added to a regular defect-prone voter to make it defect-tolerant. "Triple Modular Redundancy" (TMR) n-bit adders, made more robust in masking defects due to the use of our new voters designs, were simulated. An increase of less than 6% in transistor count and 1% in time delay were recorded for a TMR 64-bit adder compared to that based on defect-intolerant voter. Also, its power dissipation increased by less than 1% due to the added redundant transistors. Therefore the area, time delay, and power dissipation penalties, due to the added redundant transistors, are very small relative to the significant improvement of the designed circuits in tolerating permanent defects.