A Flexible Architecture for Finite Field Galois Fields(2~m) Arithmetic Processor

摘要

Elliptic Curve Cryptographic (ECC) systems have gained a lot of attention due to its excellent security strength for relatively small key sizes. The most common and computationally intensive task in an ECC system is scalar point multiplications. Arithmetic operations such as, modular multiplication, inversion, and addition in Galois Fields (GF) operands are needed to perform this task. This paper proposes an architecture for these operations on GF(2~m) operands, which could be used for various operands sizes without modifying or reconfiguring the underlying hardware. The architecture also uses power and/or clock gating techniques in order to save power in case a smaller key size is used. A 256-bit architecture was synthesized with Synopsys Design Compiler and Cadence SOC Encounter Place & Route tools using 45 nm technology. It runs at 1 GHz clock and consumes 6.6 mW. The total chip area is only 0.069 mm~2.