A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations

摘要

In this paper, a robust and energy efficient pulse-triggered flip-flop (pulsed-FF) architecture dedicated to ultra-low voltage (ULV) operations is proposed. The main innovation lays in the architecture of the pulse generator (PG) of the pulsed-FF. It allows designers to reach a robust pulsed-FF architecture without dramatic area and energy penalty. In addition, it still provides degree of freedoms to reach the best tradeoff between robustness and energy, depending on the application. Post-layout simulations proved that, for a small area penalty, the robustness of the pulsed-FF is greatly improved. In addition to that, the shareable property of the PG of pulsed-FFs at ultra-low voltage is studied in an energy point of view. It is shown that for eight or more latches sharing one PG, the energy consumption and area per flip-flop is lower than a conventional master-slave architecture.