Interconnect Aware Test Power Reduction

摘要

In Digital ICs, energy consumed in scan test cycles is known to be higher than that consumed during functional cycles. Scan-cell reordering (SCR) is a popular technique to reduce test energy consumption. Conventional SCR techniques use the number of toggles in the scan flip-flops as cost criteria for reordering. The energy consumed during the scan test cycles includes that consumed by the logic and that consumed by the scan-chain. Interconnects contribute to more than 50% of the scan-chain energy consumption. Motivated by this, the paper proposes an SCR technique that uses the wire capacitances, in addition to the toggle criteria to perform the reordering. Results obtained by employing the technique on ISCAS89 benchmarks and OpenCores show a reduction in total scan-shift energy of up to 32% and a 11 x reduction in total scan-chain wire length. It is interesting to note that just applying the SCR without considering the interconnect capacitances may lead to increase in scan-chain energy consumption in some cases. Additionally, we observe that a significant portion of the total scan-shift power comes from the first-level capacitance, contributed by both interconnects and input capacitances of gates at the first level of logic. Using this, we show that first level capacitance gating, which gates this switching capacitances of the flop-logic interconnect and first-level gates during scan-shift saves power significantly over first-level supply gating. Combining the above two methods, when applied to ISCAS89 and OpenCores benchmark circuits, we get 62% total scan-shift energy savings with a delay penalty of 3%, on the average on the functional performance of the circuit, compared to the best known algorithm.