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首页> 外文期刊>Journal of Low Power Electronics >Smart Control of Internal Supply Voltage Spikes in a Low Voltage DC-DC Buck Converter
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Smart Control of Internal Supply Voltage Spikes in a Low Voltage DC-DC Buck Converter

机译:低压DC-DC Buck转换器中内部电源电压尖峰的智能控制

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摘要

A smart dual slope gate driver for CMOS integrated low voltage DC-DC buck converters is proposed. The proposed driver reduces the switching losses and limits the magnitude of the internal voltage spikes caused by current variations on the parasitic inductances inbuilt in the converter power supply path. The dual slope gate driver has two strengths: a weak (slow) and a strong one (fast) which time duration is dynamically adjusted in order to control the time of the opening phase of the buck convertor active switch when the fastest variation of the current occurs. The magnitude of the voltage spikes in the internal power supply nodes depends on the time derivative of the current in the parasitic inductances, and can be hazardous to the chip, especially when a high current is switched at a high frequency. To overcome this problem, a common solution is to increase the turn-off time of the active switch at a cost of a reduced switching frequency and efficiency. To increase the power density of integrated low voltage DC-DC converters, the switching frequency must be increased and soft switching techniques were proposed to reduce the switching losses and to absorb the parasitic inductances and capacitances. However, these solutions increase the control complexity and cause higher voltage or current stress on the switches. Hard switching converters integrated with low voltage standard CMOS technologies can be used with high switching frequencies if new gate drivers are designed. The proposed smart dual slope gate drive reduces the internal supply voltage spikes of a DC-DC buck converter by dynamically adjusting the driver strength in order to increase the efficiency even with high switching frequencies. The dual slope drive is explained and results from a buck converter designed in a 0.13 μm standard CMOS technology are discussed in terms of the impact on high level design parameters, mainly on the switching losses and on the voltage spike magnitude reduction.
机译:提出了一种用于CMOS集成式低压DC-DC降压转换器的智能双斜率栅极驱动器。提出的驱动器减少了开关损耗,并限制了由转换器电源路径中内置的寄生电感上的电流变化引起的内部电压尖峰的幅度。双斜率栅极驱动器具有两个优势:弱(慢)和强(快),可以动态调整持续时间,以便在电流变化最快时控制降压转换器有源开关断开阶段的时间。发生。内部电源节点中电压尖峰的大小取决于寄生电感中电流的时间导数,并且可能会对芯片造成危害,尤其是在高频下切换大电流时。为了克服该问题,一种常见的解决方案是以增加的开关频率和效率为代价来增加有源开关的关断时间。为了增加集成低压DC-DC转换器的功率密度,必须提高开关频率,并提出了软开关技术来减少开关损耗并吸收寄生电感和电容。但是,这些解决方案增加了控制复杂性,并在开关上引起更高的电压或电流应力。如果设计了新的栅极驱动器,则集成有低压标准CMOS技术的硬开关转换器可以在高开关频率下使用。所提出的智能双斜率栅极驱动器通过动态调整驱动器强度来降低DC-DC降压转换器的内部电源尖峰,即使在高开关频率下也可以提高效率。解释了双斜率驱动器,并讨论了对采用0.13μm标准CMOS技术设计的降压转换器产生的结果,其中包括对高电平设计参数的影响,主要是对开关损耗和电压尖峰幅度降低的影响。

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