Improvement of Negative Bias Temperature Instability Circuit Reliability and Power Consumption Using Dual Supply Voltage

摘要

Power consumption and reliability are of great interest in modern VLSI circuits. Higher power consumption raises the circuit operating temperature that in turn worsens important reliability issues such as transistor aging due to Negative Bias Temperature Instability (NBTI). This paper proposes a design methodology for joint power consumption optimization and aging mitigation due to NBTI using Dual-Supply Voltage assignment technique. A metric based in a Figure of Merit (FM) that measures the quality of a circuit in terms of power consumption and aging-induced delay degradation is proposed. The power supply voltage level of those selected gates providing the highest benefit with the proposed metric is lowered. A trade-off between FM improvement and circuit delay penalty due to changed VDD can be stablished. The results show that the power consumption and NBTI-induced delay degradation are jointly reduced at some small delay penalty.