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IEEE 11th worshop on RTL and high level testing : digest of papers.

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1.Functional Fault Model for Micro Operation Faults of High Correlation with Stuck-At Faults

机译：高相关性与滞留故障的微操作故障的功能故障模型
- 作者：Chia Yee OOI;Hideo FUJIWARA
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- functional fauk model;
- fault coverage;
- arithmetic operations.;
2.A New Class of Acyclically Testable Sequential Circuits with Multiplexers

机译：一类新型的多路复用器可循环测试的时序电路
- 作者：Nobuya Oka;Yuki Yoshikawa;Hideyuki Ichihara;Tomoo Inoue
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- Thru testabitity;
- design for testability;
- time expansion model;
- combinational test generation algorithm.;
3.X-Identification of Transition Delay Fault Tests for Launch-off Shift Scheme

机译：发射换挡方案的过渡延迟故障测试的X标识
- 作者：K. Miyase;F.Wu;L.Dilillo;A.Bosio;P.Girard;X.Wen;S.Kajihara
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- transition delay fault;
- launch-off-shift;
- ATPG;
- X-bit;
- X-identification;
- X-filling;
4.An Optimal HDL-based Approach for Mixed-Ievel Hierarchical Fault Simulation

机译：基于最优HDL的混合流分层故障仿真方法
- 作者：Nastaran Nemati;Arezoo Kamran;MohammadHossein Sargolzaie;MohammadHashem Haghbayan;Zainalabedin Navabi
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- hierrrrchical fault simulation;
- fast fault simulation;
- concurrentfault simulation;
- HDL;
5.Network-on-Chip Concurrent Error Recovery Using Functional Switch Faults

机译：使用功能性交换机故障的片上网络并发错误恢复
- 作者：Naghmeh Karimi;Somayeh Sadeghi;Zainalabedin Navabi
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- NoC Error Recovery;
- High Level Fault Model;
6.Test Scheduling of Modular System-on-Chip under Capture Power Constraint

机译：捕获功率约束下模块化片上系统的测试调度
- 作者：Jaynarayan Tudu;Erik Larsson;Virendra Singh
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
7.Fast Detection and Analysis Schemes for System-in-Package in the Presence of RAM

机译：RAM存在下的系统级封装快速检测与分析方案
- 作者：Chia-Yi Lin;Yu-Wei Chen;Wang-Jin Chen;Hung-Ming Che
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- Interconnect;
- RAM;
- SiP;
- Test Scheme;
- Faults;
8.An Approach to Test Scheduling for Asynchronous On-Chip Interconnects Using Integer Programming

机译：一种使用整数编程的异步片上互连测试计划的方法
- 作者：Tsuyoshi Iwagaki;Eiri Takeda;Mineo Kaneko
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- Asynchronous on-chip interconnect CHAIN;
- stuck-at fault test scheduling;
- integer programming;
9.Low-Power Wrapper Design for IP Cores Based on IEEE 1500 Standard

机译：基于IEEE 1500标准的IP内核低功耗封装设计
- 作者：Yang Yu;Gang Xiang;Liyan Qiao;Dianguo Xu
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- SOC test IEEE 1500;
- test wrapper cell;
- transmission gate;
- power reduction;
10.Checking Pipelined Distributed Global Properties for Post-silicon Debug

机译：检查流水线分布的全局属性以进行硅后调试
- 作者：Erik Larsson;Bart Vermeulen;Kees Goossens
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- Validation;
- races;
- monitors;
- distributed property checking;
11.Testable and Built-In Self-Test Techniques for Motion Estimation Computing Arrays

机译：用于运动估计计算阵列的可测试的内置自检技术
- 作者：Mao- Yang Dong;Sheu-Hen Yang;Shyue-Kung Lu
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
12.A Simulation-Based Feature Selection Approach for Test Point Selection in HDL Models

机译：HDL模型中基于仿真的特征选择方法用于测试点选择
- 作者：Nastaran Nemati;Seyyed Ehsan Mahmoudi;Amirhossein Simjour;Zainalabedin Navabi
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- Test Point Insertion;
- Feature Sdection Variable Selection;
- Hardware Description Languages.;
13.SREEP-2:SR-Equivalent Generator for Secure and Testable Scan Design

机译：SREEP-2：等效于SR的发生器，用于安全且可测试的扫描设计
- 作者：Katsuya Fujiwara;Hideo Fujiwara;Hideo Tamamoto
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- design-for-tesmbility;
- scan design;
- shift register equivalents;
- security;
- scan-based side-channel attack.;
14.Clock Signal Modulation for IC Electromagnetic Compatibility

机译：时钟信号调制可实现IC电磁兼容性
- 作者：F.Lavratti;L.Bolzani;F.Vargas;J.Semi(a)o;J.Rodríguez-Andina;I.Teixeira;P.Teixeira
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- signal integrity;
- IEC 61000-4-29;
15.A Scalable Test Access Mechanism for Godson-T Multi-core Processor

机译：龙芯-T多核处理器的可扩展测试访问机制
- 作者：LuningKong;Yu Hu;XiaoweiLj
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- TAM;
- scalability;
- multi-core processor;
- wrapper;
- test pattern generation.;
16.A Comprehensive Functional Time Expansion Model Generation Method for Datapaths Using Controllers

机译：使用控制器的数据路径综合功能时间扩展模型生成方法
- 作者：Toshinori HOSOKAWA;Teppei HAYAKAWA;Masayoshi YOSHIMURA
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
17.An Approach for Verification Assertions Reuse in RTL Test Pattern Generation

机译：在RTL测试模式生成中验证声明重用的方法
- 作者：M.Jenihhin;J.Raik;R.Ubar;T.Viilukas;H.Fujiwara
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- RTL ATPG;
- assertions;
- non-scan designs;
18.Test Vector Reduction by Reordering Flip-flops for Scan Architecture with Delay Fault Testability

机译：通过对触发器进行重新排序以减少具有延迟故障可测试性的扫描架构的测试向量
- 作者：Kiyonori MATSUMOTO;Kazuteru NAMBA;Hideo ITO
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- delay fault test;
- path delay fault;
- two-pauern testing;
- scan architecture;
- Chiba-scan;
19.Multi Level Test Package A Package for C/C++ Gate Level Fault Simulation of System Level Design

机译：多级测试包用于系统级设计的C / C ++门级故障仿真的软件包
- 作者：S.Sadeghi;F.Javaheri;S.Mahmoodi;Z. Navabi
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- TLM;
- test;
- system level design;
- fault simukrtion;
- C++;
20.Test Wrapper Design for 3D System-on-Chip Using Optimized Number of TSVs

机译：使用优化数量的TSV的3D片上系统的测试包装设计
- 作者：Surajit Kumar Roy;Sourav Ghosh;Hafizur Rahaman;Chandan Giri
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- Scan chain;
- 3D integrated circuits;
- wrapper design;
- test access mechanism;
21.A Practical and Efficient Metbod to Test for Bridging Defects

机译：一种实用有效的桥接缺陷测试方法
- 作者：Cynthia Hao;Colin D.Renfrew
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- Bridging Defect;
- Fault Model;
- ATPG;
- N-detect;
- EMD;
22.VPLib: A Hybrid Method to Verify Microprocessor Prototypes on FPGA

机译：VPLib：一种在FPGA上验证微处理器原型的混合方法
- 作者：Jingfen LU;Lingkan GONG;Peng MA
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- Microprocessor Verification;
- FPGA;
- Veriflcatioon Purpose Library;
- Verification Purpose Operating System;
23.Study on Insertion Point and Area of Observation Circuit for On-Chip Debug Technique

机译：片上调试技术观察电路的插入点和面积研究
- 作者：Masayuki Arai;Yoshihiro Tabata;Kazuhiko Iwasaki
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- on-chip debug;
- sillcon debug;
- post-silicon vlidation;
- design-for-debug;
24.Transaction Level Formal Verification using Timed Automata

机译：使用定时自动机的交易级别正式验证
- 作者：A.Ghofrani;F. Javaheri;H. Noori;Z. Navabi
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- formal verification;
- timed automatta;
- transaction level modeling;
- UPPAAL;
25.Experimental Evaluation of Hybrid RTL Scan Design

机译：混合RTL扫描设计的实验评估
- 作者：Seiji Hirota;Ke Wang;Yuki Yoshikawa;Hideyuki Ichihara;Tomoo Inoue
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- RTL scan design;
- logic synthesis;
- area/delay optimization.;
26.Design for Efficient Speed-Binning and Circuit Failure Prediction and Detection

机译：高效限速和电路故障预测与检测的设计
- 作者：Songwei Pei;Huawei Li;Xiaowei Li
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- Speed-binning;
- Failweprediction;
- Failure detection;
- Stability checker;
- Binning indicator;
27.Keynote Speech Low-Power Testing for Low-Power Devices

机译：主题演讲低功耗设备的低功耗测试
- 作者：Xiaoqing Wen
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
28.Low-Power DLL-based On-Product Clock Generation for 3D Integrated Circuit Testing

机译：用于3D集成电路测试的基于低功耗DLL的产品时钟生成
- 作者：Michael Buttrick;Sandip Kundu
- 会议名称：《IEEE 11th worshop on RTL and high level testing : digest of papers.》 | 2010年
- 3D Integnated Circua Testing;
- Delay Lock Loops;
- Low Power Testing;
- On-product Clock Generation;