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Test Conference, 2004. Proceedings. ITC 2004
Test Conference, 2004. Proceedings. ITC 2004
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1.
100 DPPM in nanometer technology... is it achievable?
机译:
纳米技术的100 DPPM是可以实现的吗?
作者:
Aldrich G.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
nanotechnology;
integrated circuit design;
defective parts per million;
nanometer design technology;
process technology;
defect levels;
100 nm;
2.
A little DFT goes a long way when testing multi-Gb/s I/O signals
机译:
测试多Gb / s I / O信号时,稍加DFT就可以了
作者:
Sproch J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
production testing;
automatic test equipment;
design for testability;
DFT;
multi-Gb/s I/O signals;
manufacturing test equipment;
high speed signals;
interface specification standards;
high volume manufacturing test environment;
adaptive design techniques;
ATE configurations;
cost effective environment;
3.
Achieving quality levels of 100 DPM: it's possible... but roll up your sleeves and be prepared to do some work
机译:
达到100 DPM的质量水平:有可能……但要袖手旁观并做好准备做一些工作的准备
作者:
Nigh P.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated circuit testing;
design for testability;
integrated circuit design;
quality control;
statistical analysis;
quality levels;
delay tests;
very high coverage test patterns;
IDDQ test;
RAM tests;
multiple temperature tests;
functional test;
statistical methods;
parametric test limits;
customer specific tests;
DFT;
yield loss;
schedule impacts;
engineering costs;
4.
Achieving sub 100 DPPM defect levels on VDSM and nanometer ASICs
机译:
在VDSM和纳米ASIC上达到低于100 DPPM的缺陷级别
作者:
Benware B.R.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
nanoelectronics;
application specific integrated circuits;
design for testability;
integrated circuit reliability;
integrated circuit testing;
integrated circuit design;
fault diagnosis;
quality control;
100 DPPM defect levels;
nanometer ASIC;
structural based test;
DFT;
design for test;
scan based testing;
stuck-at fault test;
very deep submicron design;
nanometric design;
transition delay fault testing;
defect based test methods;
adaptive testing;
integrated circuit reliability;
device lifetime;
quality control;
5.
ATE value add through open data collection panel position paper for 'Dude! where's my data? - cracking open the hermetically sealed tester'
机译:
通过打开数据收集面板的位置报告中的ATE值来添加“ Dude!我的数据在哪里?-开启密封测试仪”
作者:
Madge R.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test equipment;
integrated circuit testing;
hermetic seals;
application specific integrated circuits;
field programmable gate arrays;
ATE;
open data collection;
hermetically sealed tester;
exponential rising cost;
semiconductor manufacturing;
Moore law;
ASIC;
FPGA;
mask shuttles;
semiconductor test;
yield enhancement;
fault isolation information;
impact quantification information;
6.
Board test coverage needs to be standardized
机译:
董事会测试范围需要标准化
作者:
Parker K.P.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
standardisation;
integrated circuit testing;
board test coverage;
standardisation;
PCOLA defect model;
SOQ defect model;
board manufacturers;
7.
Diagnosis meets physical failure analysis: how long can we succeed?
机译:
诊断与物理故障分析相遇:我们能成功多久?
作者:
Gattiker A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
failure analysis;
integrated circuit testing;
fault simulation;
quality assurance;
physical failure analysis;
defect detection;
quality assurance;
quality enhancement;
integrated circuit testing;
fault simulation;
8.
Diagnosis meets physical failure analysis: what is needed to succeed?
机译:
诊断与物理故障分析相结合:成功需要什么?
作者:
Venkataraman S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
failure analysis;
fault diagnosis;
integrated circuit testing;
physical failure analysis;
fault diagnosis;
root-causing failures;
IC testing;
manufacturing processes;
economic considerations;
9.
Dude! where's my data? - cracking open the hermetically sealed tester
机译:
杜德!我的资料在哪-打开密封测试仪
作者:
Daasch R.
;
Rehani M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
hermetic seals;
automatic test equipment;
profitability;
hermetically sealed tester;
ATE customers;
profitability;
process improvement;
yield improvement;
adaptive control;
product characterization;
reliability improvement;
burn-in elimination;
test floor SPC;
calibration;
test repeatability;
traditionalist camp;
mainframe camp;
Wintel camp;
red hat camp;
10.
Electronic circuit comprising a secret sub-module
机译:
包括秘密子模块的电子电路
作者:
Fleury H.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
digital circuits;
built-in self test;
logic testing;
automatic test pattern generation;
electronic circuit;
secret submodule;
digital circuit testing;
secret elements;
product life;
structural scan test;
internal registers;
functional application tests;
submodule assembly;
built-in self test circuit;
pattern generator;
11.
Functional test coverage effectiveness on the decline
机译:
功能测试覆盖范围的有效性在下降
作者:
Nejedlo J.J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
printed circuit testing;
printed circuit manufacture;
production testing;
inspection;
functional test coverage;
printed circuit boards;
defect detection;
defect migration;
board interconnect technology;
defect spectrum;
12.
Glamorous analog testability - we already test them and ship them... so what is the problem?
机译:
令人赞叹的模拟可测试性-我们已经对其进行了测试并发货...那么问题出在哪里呢?
作者:
Hafed M.M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
analogue integrated circuits;
integrated circuit testing;
integrated circuit manufacture;
design for testability;
built-in self test;
electronics industry;
test equipment;
analog testability;
analog circuits;
complex digital IC;
test practitioners;
chip manufacturers;
DFT;
BIST;
test engineers;
test equipment;
business models;
investment;
13.
Global failure localization: we have to, but on what and how?
机译:
全局故障本地化:我们必须这样做,但是在什么方面以及如何进行?
作者:
Cole E.I. Jr.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
failure analysis;
integrated circuit testing;
fault location;
global failure localization;
integrated circuits;
customers demand;
optical failure analysis techniques;
14.
How long can we succeed using the OBIRCH and its derivatives?
机译:
我们可以成功使用OBIRCH及其衍生物多长时间?
作者:
Nikawa K.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
failure analysis;
integrated circuit reliability;
automatic test equipment;
laser beam effects;
IR-OBIRCH;
infrared optical beam induced resistance change;
failure analysis tool;
semiconductor industry;
resistance change detection;
IC failure analysis;
IDDQ IC;
ATE;
automated test equipment;
15.
Investment vs. yield relationship for memories and IP in SoC
机译:
SoC中存储器和IP的投资与收益关系
作者:
Reynick J.A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
system-on-chip;
integrated circuit yield;
integrated memory circuits;
redundancy;
integrated logic circuits;
investment;
integrated circuit design;
investment;
yield relationship;
SoC designs;
IP outsourcing;
IC yield;
memory repair;
memory redundancy;
memory defect density;
higher memory percentage;
ECC methods;
standard logic;
digital circuits;
16.
Investment vs. yield relationship for memories in SOC
机译:
SOC内存中的投资与收益关系
作者:
Zorian Y.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
investment;
system-on-chip;
integrated circuit design;
integrated memory circuits;
integrated circuit yield;
investment;
SOC design;
SoC yield;
embedded memories yield;
third party sources;
memory IP provider;
collaboration;
17.
Is 'design to production' the ultimate answer for jitter, noise, and BER challenges for multi GB/s ICs?
机译:
“从设计到生产”是否是针对多GB / s IC的抖动,噪声和BER挑战的最终答案?
作者:
Li M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated circuit testing;
timing jitter;
integrated circuit noise;
error statistics;
design to production;
BER;
ITC 2003;
Multi-GB/s IC Test Challenges and Solutions;
IC manufacture;
ATE industries;
timing jitter;
amplitude noise;
high volume manufacture;
18.
Is 'Heisenberg uncertainty principle' hold for designing and testing multiple Gb/s ICs ?
机译:
“海森堡不确定性原理”是否适用于设计和测试多个Gb / s IC?
作者:
Li M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated circuit design;
integrated circuit testing;
jitter;
error statistics;
indeterminancy;
production testing;
Heisenberg uncertainty principle;
integrated circuit design;
integrated circuit testing;
statistical process;
jitter;
noise;
bit error rate;
design simulation;
high volume manufacturing test;
cost minimisation;
design characterization;
design verification;
19.
ITC 2004 panel: cost of test - taking control Mike Tripp Intel Corporation
机译:
ITC 2004小组:测试成本-控制权Mike Tripp英特尔公司
作者:
Tripp M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
quality control;
design for testability;
microprocessor chips;
cost reduction;
design for manufacture;
product design;
integrated circuit design;
integrated circuit testing;
ITC 2004 panel;
Mike Tripp Intel Corporation;
testing cost;
quality cost;
quality goals;
cost minimization;
DFT;
HVM products;
low capability testers;
DFM requirements;
product definition;
product design;
predictive models;
microprocessor chips;
integrated circuit design;
integrated circuit testing;
20.
Loopback or not? (loopback testing)
机译:
回送还是不回送? (环回测试)
作者:
Yamaguchi T.J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated circuit testing;
timing jitter;
sampling methods;
loopback testing;
high speed serial I/O devices;
equivalent time sampling method;
ultra wideband jitter;
multi-Gb/s physical layer IC;
jitter tolerance testing;
jitter measurement;
21.
Memory yield improvement - SoC design perspective
机译:
内存产量提高-SoC设计观点
作者:
Khare J.B.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
system-on-chip;
integrated circuit design;
integrated circuit yield;
integrated memory circuits;
design for manufacture;
redundancy;
cost reduction;
memory yield improvement;
on-chip memories;
SoC design;
redundancy;
DFM based bit cell design;
metal layers;
die cost reduction;
foundry;
IP companies;
22.
Open architecture ATE: dream or reality?
机译:
开放式架构ATE:梦想还是现实?
作者:
Robinson G.D.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test equipment;
open systems;
open architecture ATE;
semiconductor ATE systems;
instrument standards;
23.
Open architecture ATE: prospects and problems
机译:
开放架构ATE:前景和问题
作者:
West B.G.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test equipment;
cost reduction;
open systems;
open architecture ATE;
cost reduction;
value enhancement;
open architecture platforms;
DUT board interface;
synchronization;
DUT fixturing assignments;
24.
Options for high-volume test of multi-Gb/s ports
机译:
大量测试多Gb / s端口的选项
作者:
Johnson J.C.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test equipment;
logic testing;
high-volume test;
multiports;
PCI Express;
serial-parallel port technology;
bandwidth scaling;
PCB trace out;
SERDES devices;
ATE instruments;
physical layer compliance testing;
logic test patterns;
very high speed interfaces;
nondeterministic logic behavior;
25.
Panel 7 : cost of test - taking control failure mechanism
机译:
第7组:测试成本-采取控制措施故障机制
作者:
Mukherjee N.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
nanotechnology;
failure analysis;
fault diagnosis;
nanometer technology;
failure mechanisms;
defects per million;
silicon manufacturers;
structural test vectors;
defect rate reduction;
fault models;
stuck-at faults;
26.
Panel 9 - diagnostics vs failure analysis
机译:
面板9-诊断与故障分析
作者:
Bartenstein T.W.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated circuit testing;
failure analysis;
fault diagnosis;
automatic test pattern generation;
logic testing;
physical failure analysis;
diagnostic tools;
chip failure;
chip defect identification;
logic model environment;
ATPG technology;
data collection;
photon emission tool;
virtual failure analysis;
inline defect data;
27.
Panel synopsis - diagnosis meets physical failure analysis: how long can we succeed?
机译:
小组简介-诊断与物理故障分析相结合:我们能成功多久?
作者:
Okuda Y.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
silicon;
elemental semiconductors;
failure analysis;
fault simulation;
production testing;
physical failure analysis;
faulty devices;
yield improvement;
production testing;
silicon debugging;
fault diagnosis;
external signatures;
failure hypothesis;
28.
Plan ahead for yield
机译:
提前计划产量
作者:
Jun Qian
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
redundancy;
integrated circuit yield;
application specific integrated circuits;
integrated memory circuits;
time to market;
time to market;
silicon yield;
redundancy plan;
random logic;
memory yield;
ASIC;
29.
Redefining ATE: 'data collection engines that drive yield learning and process optimization'
机译:
重新定义ATE:“推动良率学习和流程优化的数据收集引擎”
作者:
Nigh P.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test equipment;
integrated circuit yield;
integrated circuit testing;
circuit optimisation;
ATE requirements;
data collection engines;
yield learning rate;
process optimization;
IC producers;
product lifetime;
IC suppliers;
30.
Security vs. test quality: are they mutually exclusive?
机译:
安全性与测试质量:它们是否互斥?
作者:
Kapur R.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
design for testability;
integrated circuit testing;
cryptography;
scan technology;
IP theft;
scan chains;
DFT;
design for testability;
decryption;
encryption;
integrated circuit testing;
high quality testing;
31.
Security vs. test quality: can we really only have one at a time?
机译:
安全性与测试质量:我们真的一次只能拥有一个吗?
作者:
Marinissen E.J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated circuit design;
integrated circuit testing;
integrated circuit manufacture;
design for testability;
electronics industry;
security of data;
industrial property;
virtual reality;
on-chip data security;
manufacturing test quality;
personal integrity;
virtual money;
controllability;
observability;
high tech hackers;
intellectual property;
IC design;
design-for-testability hardware;
product quality;
secure industry;
32.
Security vs. test quality: fully embedded test approaches are the key to having both
机译:
安全性与测试质量:完全嵌入式测试方法是同时拥有这两种方法的关键
作者:
Pateras S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
logic testing;
automatic test pattern generation;
built-in self test;
fully embedded at-speed structural test;
random logic testing;
full scan ATPG method;
ATPG compression;
logic BIST method;
IP protection;
external scan test data;
33.
Sure you can get to 100 DPPM in deep submicron, but it'll cost ya
机译:
当然,您可以达到100 DPPM的深亚微米级,但要花费您
作者:
Butler K.M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test pattern generation;
statistical analysis;
integrated circuit testing;
fault diagnosis;
defective parts per million;
sub-100 DPPM numbers;
deep submicron technology;
fault models;
probabilistic approach;
statistical approach;
tester;
on-chip pattern compression schemes;
test generation;
34.
Test strategies for nanometer technologies
机译:
纳米技术的测试策略
作者:
Sengupta S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
nanoelectronics;
system-on-chip;
quality control;
design for testability;
integrated circuit design;
integrated circuit testing;
stochastic processes;
built-in self test;
nanometer technology;
systems-on-chip;
die size;
double-digit DPM;
quality control;
nanometer process;
delay defects;
process variation;
functional testing;
high coverage scan content;
yield losses;
DFT;
at-speed test application methods;
subtle defect types;
stochastic process;
N-defect process;
BIST;
35.
Testing a secure device: high coverage with very low observability
机译:
测试安全设备:可观察性极低的高覆盖范围
作者:
Sourgen L.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
microcontrollers;
system-on-chip;
built-in self test;
integrated circuit testing;
secure device testing;
microcontrollers;
smart card;
system on chip;
circuit protection;
standard structural testing;
scan testing;
functional testing;
BIST;
antileakage dedicated functions;
antitampering dedicated functions;
36.
Testing in a high volume DSM environment
机译:
在大容量DSM环境中进行测试
作者:
Storey T.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
built-in self test;
design for manufacture;
automatic test equipment;
integrated circuit testing;
deep sub micron environment;
deep sub micron design;
design for manufacturability;
testing;
ATE;
at-speed BIST techniques;
37.
The critical need for open ATE architecture
机译:
开放式ATE架构的迫切需求
作者:
Perez S.M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test equipment;
integrated circuit testing;
time to market;
electronics industry;
design for testability;
built-in self test;
cost reduction;
open ATE architecture;
ATE systems;
IC test solutions;
time to market;
design for testability;
built-in-self test;
semiconductor industry;
38.
To test or to inspect, what is the coverage?
机译:
测试或检查范围是什么?
作者:
Jukna R.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
inspection;
integrated circuit testing;
manufacturing processes;
production testing;
standardisation;
inspection;
test engineering community;
standardisation;
in-circuit test;
manufacturing process;
board test coverage;
single test process;
defect coverage;
39.
What do you mean by board test stinks?
机译:
董事会测试臭味是什么意思?
作者:
Smith J.M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
printed circuit testing;
X-ray applications;
integrated circuit testing;
electrical faults;
automatic optical inspection;
board test stinks;
printed circuit board manufacturing;
in-circuit test;
electrical test system;
electrical faults;
manufacturing faults;
automatic optical inspection;
automatic X-ray inspection;
40.
What do you mean my board test stinks?
机译:
您的董事会考试有什么臭味?
作者:
Eklow B.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated circuit testing;
application specific integrated circuits;
board level testing;
system level testing;
structural testing;
functional testing;
parametric testing;
assembly process;
bit error rate;
jitter;
application specific integrated circuits;
41.
Practical instrumentation integration considerations
机译:
实用仪器集成注意事项
作者:
Anderson T.J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test equipment;
built-in self test;
boundary scan testing;
integrated circuit testing;
instrumentation integration;
BIST;
SCAN;
test time minimization;
cost minimization;
AC parametric test;
DC parametric test;
signal integrity problems;
ATE;
capacitive loading;
resistive loading;
bandwidth;
phase matching;
calibration;
thermal drift;
trouble free integration;
42.
An economic analysis and ROI model for nanometer test
机译:
用于纳米测试的经济分析和ROI模型
作者:
Keller B.
;
Tegethoff M.
;
Bartenstein T.
;
Chickermane V.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
nanoelectronics;
logic testing;
investment;
integrated logic circuits;
integrated circuit testing;
integrated circuit economics;
economic analysis;
return on investment model;
nanometer test;
test methodology;
product quality;
logic devices;
integrated circuit testing;
130 nm;
43.
At-speed interconnect test and diagnosis of external memories on a system
机译:
快速互连测试和系统上外部存储器的诊断
作者:
Kim H.C.
;
Jun H.-S.
;
Xinli Gu
;
Chung S.S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
built-in self test;
SRAM chips;
DRAM chips;
boundary scan testing;
integrated circuit interconnections;
integrated circuit testing;
design for testability;
logic testing;
at-speed interconnect test;
at-speed interconnect diagnosis;
external memories;
built-in self test;
double data rate;
quad data rate;
SRAM;
fast cycle RAM;
reduced latency DRAM;
fixed latency memory controller;
functional interface protocols;
handshake memory controllers;
BIST architecture;
boundary scan driven BIST operation;
system level test;
system level diagnosis;
system clock;
system hard reset;
soft reset;
BIST functions;
system mission operation;
design for testability;
44.
Elimination of traditional functional testing of interface timings at Intel
机译:
消除了英特尔接口时序的传统功能测试
作者:
Tripp M.
;
Mak T.M.
;
Meixner A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
design for testability;
integrated circuit design;
integrated circuit testing;
microprocessor chips;
automatic test equipment;
peripheral interfaces;
high-speed integrated circuits;
functional testing elimination;
interface timings;
Intel Pentium/sup /spl reg// 4 processor;
DFT circuitry;
design for test;
ATE;
automatic test equipment;
lower capability structural test platforms;
circuit implementations;
HVM data;
high volume manufacturing data;
high speed serial interfaces;
45.
Fault tolerant arithmetic with applications in nanotechnology based systems
机译:
容错算法及其在基于纳米技术的系统中的应用
作者:
Wenjing Rao
;
Orailoglu A.
;
Karri R.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
nanoelectronics;
fault tolerance;
block codes;
error correction codes;
redundant number systems;
linear codes;
arithmetic codes;
carry logic;
negative resistance;
negative resistance circuits;
fault tolerant arithmetic operations;
nanotechnology based systems;
negative differential resistance characteristics;
multivalued logic states;
native digit level carry save arithmetic;
native digit level redundant number system;
linear block codes;
error checking codes;
error correction codes;
nanoelectronic environment;
digit level information redundancy;
fault tolerant communications;
storage systems;
storage subsystems;
46.
Impact of body bias on delay fault testing of nanoscale CMOS circuits
机译:
体偏置对纳米级CMOS电路延迟故障测试的影响
作者:
Paul B.C.
;
Neau C.
;
Roy K.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
CMOS integrated circuits;
integrated circuit testing;
microprocessor chips;
statistical analysis;
fault diagnosis;
low-power electronics;
delay fault testing;
nanoscale CMOS circuits;
microprocessors;
forward body bias;
leakage power reduction;
adaptive body biasing design;
test cost minimisation;
statistical analysis;
test quality;
process variation;
dual V/sub th/ technology;
benchmark circuits;
100 nm;
47.
Integrating boundary scan into multi-GHz I/O circuitry
机译:
将边界扫描集成到多GHz I / O电路中
作者:
Rearick J.
;
Patterson S.
;
Dorner K.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
silicon;
system-on-chip;
elemental semiconductors;
IEEE standards;
integrated circuit testing;
boundary scan testing;
high-speed integrated circuits;
microwave integrated circuits;
minimally invasive solution;
multi-GHz I/O circuitry;
high speed I/O circuits;
boundary scan registers;
lower speed parallel domain;
high speed serial domain;
silicon testing;
IEEE 1149.1 standards;
IEEE 1149.6 standards;
microwave integrated circuits;
48.
Low cost concurrent error detection for the advanced encryption standard
机译:
用于高级加密标准的低成本并发错误检测
作者:
Wu K.
;
Ramesh Karri
;
Kuznetsov G.
;
Goessel M.
会议名称:
《》
|
2004年
关键词:
error detection;
cryptography;
fault diagnosis;
field programmable gate arrays;
delays;
low cost concurrent checking method;
error detection;
advanced encryption standard;
encryption algorithm;
parity modifications;
Xilinx Virtex 1000 FPGA;
time delay;
fault detection;
128 bit;
49.
Non-deterministic DUT behavior during functional testing of high speed serial busses: challenges and solutions
机译:
高速串行总线功能测试期间不确定的DUT行为:挑战和解决方案
作者:
Hops J.
;
Swing B.
;
Phelps B.
;
Sudweeks B.
;
Pane J.
;
Kinslow J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
peripheral interfaces;
automatic test equipment;
high-speed integrated circuits;
integrated circuit testing;
functional testing;
high speed serial busses;
PCI Express busses;
ATE architecture;
nondeterministic DUT behavior;
RapidIO/sup /spl reg// bus;
real time pass-fail analysis;
50.
On correlating structural tests with functional tests for speed binning of high performance design
机译:
将结构测试与功能测试相关联以加快高性能设计的装箱速度
作者:
Zeng J.
;
Abadir M.
;
Vandling G.
;
Wang L.
;
Kolhatkar A.
;
Abraham J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated circuit testing;
integrated circuit design;
microprocessor chips;
high-speed integrated circuits;
automatic test pattern generation;
structural testing;
functional test frequency;
speed binning;
high performance IC;
functional testing;
structural patterns;
MPC7455 processor;
Motorola processor;
PowerPC/spl trade/ instruction set architecture;
51.
Simulation based system level fault insertion using co-verification tools
机译:
使用协同验证工具基于仿真的系统级故障插入
作者:
Eklow B.
;
Hosseini A.
;
Chi Khuong
;
Pullela S.
;
Vo T.
;
Chau H.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
fault simulation;
hardware description languages;
simulation based system level fault insertion;
co-verification tools;
simulation based environment;
fault insertion environment;
Verilog model;
co-verification platform;
system level software;
fault manager;
diagnostic messages;
fault diagnosis;
fault detection;
resource requirements;
52.
Time/area tradeoffs in testing hierarchical SOCs with hard mega-cores
机译:
使用硬大核测试分层SOC的时间/区域权衡
作者:
Qiang Xu
;
Nicolici N.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
system-on-chip;
integrated circuit design;
integrated circuit testing;
time-area tradeoffs;
hierarchical SOC testing;
hierarchical systems-on-a-chip;
hard mega cores;
design space exploration;
multilevel test access mechanisms;
mega core wrappers;
53.
Verification on port connections
机译:
验证端口连接
作者:
Geeng-Wei Lee
;
Chun-Yao Wang
;
Juinn-Dar Huang
;
Jing-Yang Jou
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
system-on-chip;
integrated circuit design;
integrated circuit interconnections;
integrated circuit testing;
system-on-chip design;
SOC design;
port connection verification;
intellectual properties;
integrated IP;
error model;
minimum pattern set;
connection model;
54.
34.1 Gbps low jitter, low BER high-speed parallel CMOS interface for interconnections in high-speed memory test system
机译:
34.1 Gbps低抖动,低BER高速并行CMOS接口,用于高速存储器测试系统中的互连
作者:
Watanabe D.
;
Suda M.
;
Okayasu T.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test equipment;
jitter;
error statistics;
application specific integrated circuits;
digital phase locked loops;
CMOS memory circuits;
clocks;
high speed memory test system;
high speed parallel CMOS interface macro;
ATE systems;
ASIC;
ultralow BER;
low jitter digital delay locked loop circuit;
SerDes circuits;
4 phase clock source;
PLL;
transmitter channel;
receiver channel;
34.1 Gbit/s;
2.13 Gbit/s;
55.
A novel scan chain diagnostics technique based on light emission from leakage current
机译:
基于泄漏电流发光的新型扫描链诊断技术
作者:
Song P.
;
Stellari F.
;
Xia T.
;
Weger A.J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated circuit design;
integrated circuit testing;
CMOS integrated circuits;
VLSI;
flip-flops;
leakage currents;
microprocessor chips;
fault diagnosis;
design for testability;
scan chain diagnostics technique;
light emission;
offstate leakage current;
VLSI designs;
latches;
flip flops;
microprocessors;
CMOS technology;
chip design;
chip packaging;
chip cooling;
VLSI circuit testing;
VLSI circuit diagnosis;
defect localization;
56.
A real-time jitter measurement board for high-performance computer and communication systems
机译:
用于高性能计算机和通信系统的实时抖动测量板
作者:
Yamaguchi T.J.
;
Ishida M.
;
Soma M.
;
Ichiyama K.
;
Christian K.
;
Ohsawa K.
;
Sugai M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
timing jitter;
digital communication;
transceivers;
production testing;
cost reduction;
real time jitter measurement board;
high performance computer systems;
high performance communication systems;
high frequency clocks;
data transceivers;
high volume manufacturing test;
sinusoidal jitter tolerance;
random jitter;
cost reduction;
production testing;
57.
ALAPTF: a new transition fault model and the ATPG algorithm
机译:
ALAPTF:一种新的过渡故障模型和ATPG算法
作者:
Gupta P.
;
Hsiao M.S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test pattern generation;
integrated circuit testing;
delays;
fault diagnosis;
as late as possible transition fault model;
ATPG algorithm;
path delay model;
ISCAS89 benchmark circuits;
ISCAS85 benchmark circuits;
gate delay detection;
linear execution time;
delay defects;
robust path detection;
nonrobust path detection;
58.
Data mining integrated circuit fails with fail commonalities
机译:
数据挖掘集成电路因通用性而失败
作者:
Huisman L.M.
;
Kassab M.
;
Pastel L.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
data mining;
integrated circuit reliability;
failure analysis;
data mining;
integrated circuit fails;
fail commonalities;
failure diagnosis;
standard diagnostic routines;
59.
Embedded test for a new memory-card architecture
机译:
对新存储卡体系结构的嵌入式测试
作者:
Resnick D.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
memory cards;
memory architecture;
Cray computers;
integrated circuit testing;
embedded systems;
logic testing;
peripheral interfaces;
microcontrollers;
memory card architecture;
embedded test system;
Cray computer system;
high speed serializer deserializer interfaces;
multiple memory controllers;
semicustom IC;
memory chips;
memory testers;
JTAG port;
joint test action group standard;
microcoded controller;
data packets;
logic control;
logic testing;
60.
Evaluating the effects of transient faults on vehicle dynamic performance in automotive systems
机译:
评估瞬态故障对汽车系统中车辆动态性能的影响
作者:
Corno F.
;
Esposito F.
;
Sonza Reorda M.
;
Tosato S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automotive electronics;
automotive components;
vehicle dynamics;
failure analysis;
safety;
transient response;
fault diagnosis;
transient faults effects;
vehicle dynamic performance;
automotive systems;
electronic components failure;
electronic network failures;
vehicle stability;
vehicle safety;
mechanical components;
fault injection environment;
61.
IEEE standard 1149.6 implementation for a XAUI-to-serial 10-Gbps transceiver
机译:
XAUI到串行10 Gbps收发器的IEEE标准1149.6实现
作者:
Shaikh S.A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
IEEE standards;
transport protocols;
current-mode logic;
circuit CAD;
boundary scan testing;
transceivers;
logic testing;
nanoelectronics;
IEEE standard 1149.6 IP;
XAUI to serial 10-Gbps transceiver;
current mode logic;
CML;
input test receiver;
boundary scan register;
AC boundary scan cells;
output test signal generation circuitry;
TAP controller;
CAD tools;
IEEE standard 1149.1 IP generation;
90 nm;
10 Gbit/s;
62.
Impact of negative bias temperature instability on product parametric drift
机译:
负偏置温度不稳定性对产品参数漂移的影响
作者:
Reddy V.
;
Carulli J.
;
Krishnan A.
;
Bosch W.
;
Burgess B.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
thermal stability;
MOSFET;
semiconductor device reliability;
integrated circuit reliability;
CMOS digital integrated circuits;
negative bias temperature instability;
product parametric drift;
test guard banding technique;
parameter drift estimation;
transistors;
degradation mechanisms;
digital CMOS circuits;
63.
Jitter models and measurement methods for high-speed serial interconnects
机译:
高速串行互连的抖动模型和测量方法
作者:
Kuo A.
;
Farahmand T.
;
Ou N.
;
Tabatabaei S.
;
Ivanov A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
jitter;
error statistics;
crosstalk;
telecommunication links;
data communication;
probability;
jitter models;
jitter measurement methods;
high speed serial interconnects;
jitter subcomponents;
jitter PDF;
BER;
bit error rate;
bounded uncorrelated jitter;
crosstalk;
serial communication link;
64.
Localizing open interconnect defects using targeted routing in FPGA's
机译:
在FPGA的目标布线中定位开放式互连缺陷
作者:
Mark D.
;
Fan J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
field programmable gate arrays;
network routing;
fault location;
logic testing;
open interconnect defect localization;
targeted routing;
FPGA;
open metal interconnects fault localization;
open metal interconnects fault detection;
metal defect isolation;
metal interconnect layers;
physical defect location;
metal bridging defect detection;
logic testing;
65.
Post-packaging auto repair techniques for fast row cycle embedded DRAM
机译:
用于快速行周期嵌入式DRAM的打包后自动修复技术
作者:
Wada O.
;
Namekawa T.
;
Ito H.
;
Nakayama A.
;
Fujii S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
DRAM chips;
integrated circuit testing;
logic testing;
post-packaging auto repair technique;
fast row cycle embedded DRAM;
conventional wafer testing;
post-package test;
internal compare circuit;
redundancy analyzer;
anti-fuses;
internal auto programming;
post-packaging failures;
at-speed test;
6 ns;
66.
Power supply ramping for quasi-static testing of PLLs
机译:
电源斜坡用于PLL的准静态测试
作者:
Pineda de Gyvez J.
;
Gronthoud G.
;
Cenci C.
;
Posch M.
;
Burger T.
;
Koller M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
phase locked loops;
power supply circuits;
circuit feedback;
production testing;
integrated circuit testing;
fault diagnosis;
logic testing;
power supply ramping;
quasistatic testing;
open loop mode;
PLL power supply;
periodic sawtooth signal;
feedback inputs;
clock reference signal;
oscillator control voltage;
fault coverage;
production wafer testing;
structural testing;
67.
Precise pulse width measurement in write pre-compensation test
机译:
写入预补偿测试中的精确脉冲宽度测量
作者:
Okawara H.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
magnetic heads;
pulse measurement;
hard discs;
disc drives;
intersymbol interference;
fast Fourier transforms;
pulse width measurement;
write precompensation test;
bit density;
hard disk drives;
magnetic media;
intersymbol interference;
write data timing;
pulse width modification;
device manufacturers;
clock stream generation;
time interval analyzers;
analog bandwidth;
DC signal offset;
waveform sampler;
frequency component;
pulse width increments;
data processing;
fast Fourier transform;
68.
Removing JTAG bottlenecks in system interconnect test
机译:
消除系统互连测试中的JTAG瓶颈
作者:
Hong-Shin Jun
;
Chung S.S.
;
Baeg S.H.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated circuit testing;
integrated circuit interconnections;
logic testing;
synchronisation;
cluster tools;
boundary scan testing;
automatic test pattern generation;
JTAG bottlenecks;
system interconnect test;
JTAG test;
low-speed testing;
system clock;
network cluster;
skew properties;
delay properties;
synchronization;
high speed pattern clock;
high frequency interconnection testing;
cluster testing;
delay testing;
test vehicles;
differential signal lines;
AC coupling interconnections;
latency interconnections;
optical signal interconnections;
boundary scan testing;
69.
RF testing on a mixed signal tester
机译:
在混合信号测试仪上进行射频测试
作者:
Brown D.
;
Ferrario J.
;
Wolf R.
;
Li J.
;
Bhagat J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
Global Positioning System;
automatic test equipment;
mixed analogue-digital integrated circuits;
radiofrequency integrated circuits;
integrated circuit testing;
RF testing;
mixed signal tester;
radio frequency devices;
automatic test equipment;
global positioning system;
70.
Simulation requirements for vectors in ATE formats
机译:
ATE格式的矢量的仿真要求
作者:
Raghuraman R.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test equipment;
built-in self test;
integrated circuit testing;
failure analysis;
test vector simulation;
ATE formats;
failure diagnosis;
failure prevention;
BIST;
71.
Test cost reduction through a reconfigurable scan architecture
机译:
通过可重新配置的扫描架构降低测试成本
作者:
Arslan B.
;
Orailoglu A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated memory circuits;
boundary scan testing;
integrated circuit testing;
reconfigurable architectures;
automatic test pattern generation;
cost reduction;
circuit complexity;
integrated circuit design;
test cost reduction;
reconfigurable scan architecture;
scan based designs;
test generation complexity;
circular structure;
integrated memory circuits;
72.
Testing and remote field update of distributed base stations in a wireless network
机译:
无线网络中分布式基站的测试和远程现场更新
作者:
Chen-Huan Chiang
;
Wheatley P.J.
;
Ho K.Y.
;
Cheung K.L.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
radio access networks;
boundary scan testing;
distributed processing;
computer architecture;
microcomputers;
PROM;
distributed system testing;
remote field update;
distributed base stations;
wireless network services;
distributed test architecture;
IEEE 1149.1 boundary scan signals;
test access port signals;
serial channel;
installation cost;
operation cost;
space requirements;
boundary scan test software;
microprocessor;
programmable ROM;
slow-fast programming algorithm;
fiber propagation delay;
73.
Towards microagent based DBIST/DBISR
机译:
迈向基于微代理的DBIST / DBISR
作者:
Miclea L.
;
Enyedi S.
;
Toderean G.
;
Benso A.
;
Prinetto P.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
built-in self test;
multi-agent systems;
Java;
fault diagnosis;
microagent based distributed BIST;
built in self test;
microagent based distributed BISR;
built in self repair;
distributed system;
embedded BIST;
embedded BISR;
software modules;
fault monitoring;
fault diagnosis;
fault repair;
mobile tester microagents;
Java 2 Micro Edition;
BREW;
Symbian;
PalmOS;
74.
Within die thermal gradient impact on clock-skew: a new type of delay-fault mechanism
机译:
内部热梯度对时钟偏移的影响:一种新型的延迟故障机制
作者:
Bota S.A.
;
Rosales M.
;
Rosello J.L.
;
Keshavarzi A.
;
Segura J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
digital integrated circuits;
integrated circuit testing;
high-speed integrated circuits;
temperature distribution;
fault diagnosis;
clocks;
delays;
die thermal gradients;
delay fault mechanism;
die thermal map distribution;
test mode operations;
normal mode operations;
test induced hot spots;
clock delay testing;
nonuniform thermal induced delay;
clock circuitry;
zero skew clock routing algorithms;
thermal map temperature;
clock tree speed;
delay test patterns;
75.
A design for test technique for parametric analysis of SRAM: on-die low yield analysis
机译:
SRAM参数分析的测试技术设计:片上低产量分析
作者:
Mauck B.M.
;
Ravichandran V.
;
Mughal U.A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
design for testability;
integrated circuit testing;
failure analysis;
semiconductor process modelling;
SRAM chips;
CMOS integrated circuits;
design for test technique;
parametric analysis;
SRAM;
on-die low yield analysis;
microprocessor;
fault isolation;
failure analysis;
CMOS process technology;
transistors;
leakage distortion;
scaling process technology;
65 nm;
76.
A frequency mixing and sub-sampling based RF-measurement apparatus for IEEE 1149.4
机译:
用于IEEE 1149.4的基于混频和子采样的RF测量设备
作者:
Hakkinen J.
;
Syri P.
;
Voutilainen J.-V.
;
Moilanen M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
microwave measurement;
IEEE standards;
signal generators;
voltage-controlled oscillators;
measurement uncertainty;
measurement systems;
frequency measurement;
frequency mixing method;
frequency subsampling method;
RF measurement apparatus;
radio frequency measurements;
IEEE 1149.4 environment;
RF signal sources;
analogue busses;
1149.4 standard;
RF signal generators;
VCO;
RF to LF circuitry;
analog test access device;
RF power measurement;
measurement uncertainty;
measurement instruments;
interconnect measurements;
SCANSTA400 device;
2 GHz;
3 GHz;
2.1 GHz;
77.
A model-based test approach for testing high speed PLLs and phase regulation circuitry in SOC devices
机译:
基于模型的测试方法,用于测试SOC器件中的高速PLL和相位调节电路
作者:
Laquai B.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
system-on-chip;
digital phase locked loops;
high-speed integrated circuits;
integrated circuit testing;
integrated circuit modelling;
integrated circuit design;
automatic test equipment;
clocks;
jitter;
fault diagnosis;
frequency-domain analysis;
model based test method;
high speed PLL;
phase locked loops;
phase regulation circuitry;
SOC devices;
gigahertz clocks on chip;
data signals;
high speed IO links;
fault coverage;
jitter performance;
specification oriented test methods;
ATE;
frequency domain model;
design phase regulation characteristics;
leading edge measurement equipment;
BERT;
parametric defects;
78.
A modular wrapper enabling high speed BIST and repair for small wide memories
机译:
模块化包装器可实现高速BIST和修复小范围内存
作者:
Aitken R.C.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
built-in self test;
integrated circuit testing;
high-speed integrated circuits;
integrated circuit design;
integrated memory circuits;
logic testing;
modular wrapper design;
high speed BIST controller;
high speed BISR;
small wide memories;
register files;
FIFO;
high speed applications;
wrapper at-speed test;
test controller;
integrated circuit testing;
logic testing;
79.
Analysis of delay caused by bridging faults in RLC interconnects
机译:
RLC互连中的桥接故障导致的延迟分析
作者:
Zhou Q.
;
Mohanram K.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
RLC circuits;
integrated circuit interconnections;
integrated circuit modelling;
fault diagnosis;
SPICE;
circuit simulation;
delay analysis;
resistive bridging defects;
inductive effects;
capacitive effects;
logic errors;
extra switching delay;
distributed RLC interconnect model;
closed form RLC model;
interconnect lines;
SPICE;
fault diagnosis;
circuit simulation;
80.
ATE data collection - a comprehensive requirements proposal to maximize ROI of test
机译:
ATE数据收集-全面的需求建议,以最大化测试的投资回报率
作者:
Rehani M.
;
Abercrombie D.
;
Madge R.
;
Teisher J.
;
Saw J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test equipment;
ATE data collection;
ROI maximization;
ATE customers;
profitability;
statistical post processing;
die binning;
reliability;
burn-in elimination;
process yield improvement;
adaptive control;
product characterization;
test floor statistical process control;
ATE vendor;
measurement evaluation;
state of the art technology;
81.
Controlled sine wave fitting for ADC test
机译:
用于ADC测试的可控正弦波拟合
作者:
Mattes H.
;
Sattler S.
;
Dworski C.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
analogue-digital conversion;
integrated circuit testing;
mixed analogue-digital integrated circuits;
built-in self test;
hardware description languages;
field programmable gate arrays;
circuit complexity;
circuit simulation;
fast Fourier transforms;
controlled sine wave fitting;
ADC test response;
analog to digital converters test;
dynamic parameters;
time domain;
built-in self-test;
BIST;
mixed signal circuits;
circuit complexity;
VHDL code;
field programmable gate array;
FPGA;
Teradyne J750 tester;
circuit simulation;
FFT based methods;
test time reduction;
82.
Defect coverage analysis of partitioned testing
机译:
分区测试的缺陷覆盖率分析
作者:
Chakravarty S.
;
Savage E.W.
;
Tran E.N.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
automatic test pattern generation;
fault diagnosis;
integrated circuit testing;
defect coverage analysis;
test quality improvement;
fault models;
coverage metrics;
test pattern generation;
product quality;
quiescent state;
test sequence generation;
functional pattern quality;
functional testing;
83.
Efficient pattern mapping for deterministic logic BIST
机译:
确定性逻辑BIST的有效模式映射
作者:
Gherman V.
;
Wunderlich H.-J.
;
Vranken H.
;
Hapke F.
;
Wittke M.
;
Garbers M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
built-in self test;
logic testing;
integrated circuit testing;
binary decision diagrams;
circuit complexity;
efficient pattern mapping;
deterministic logic BIST;
deterministic external testing;
pseudorandom logic BIST;
linear complexity;
memory consumption;
BDD;
binary decision diagrams;
84.
Extending STIL 1450 standard for test program flow
机译:
扩展STIL 1450标准以用于测试程序流程
作者:
Dowding D.
;
Wahl E.
;
Organ D.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
IEEE standards;
automatic test equipment;
time to market;
automatic test pattern generation;
design for testability;
STIL 1450 standard;
IEEE P1450.4;
test program flow extension;
design to test automation tools;
portability;
ATE platforms;
semiconductor industry;
time to market;
program generation;
85.
Extending the digital core-based test methodology to support mixed-signal
机译:
扩展基于数字核的测试方法以支持混合信号
作者:
Seuren G.
;
Waayers T.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
mixed analogue-digital integrated circuits;
system-on-chip;
integrated circuit testing;
design for testability;
integrated circuit design;
digital core based test architecture;
mixed signal cores testing;
system-on-chip;
test library;
DFT;
86.
How to bridge the gap between simulation and test
机译:
如何弥合仿真与测试之间的鸿沟
作者:
Zambaldi M.
;
Ecker W.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated circuit testing;
automatic test pattern generation;
hardware description languages;
integrated circuit modelling;
tester related simulation environment;
transforming simulation element;
interface pattern;
test programs;
e-beam analysis;
synchronous communication;
asynchronous communication;
unit under verification;
hardware description language;
87.
Improving encoding efficiency for linear decompressors using scan inversion
机译:
使用扫描反演提高线性解压缩器的编码效率
作者:
Balakrishnan K.J.
;
Touba N.A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
encoding;
combinational circuits;
sequential circuits;
linear algebra;
Boolean algebra;
matrix algebra;
encoding efficiency;
linear decompressors;
scan inversion;
linear transformation;
Boolean matrix;
linear algebra;
combinational decompressor;
sequential decompressor;
test cubes;
88.
IPv6 conformance testing: theory and practice
机译:
IPv6一致性测试:理论与实践
作者:
Yujun Zhang
;
Zhongcheng Li
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
IP networks;
transport protocols;
conformance testing;
software reliability;
specification languages;
IPv6 conformance testing;
protocols;
IPv6 devices;
IPv6 reliability;
IPv6 test requirements;
test packets description;
IPv6 test framework;
IPv6 test suite specification language;
virtual test method;
low layer congregating test method;
89.
Jitter generation and measurement for test of multi-Gbps serial IO
机译:
抖动生成和测量,用于测试多Gbps串行IO
作者:
Tabatabaei S.
;
Lee M.
;
Ben-Zeev F.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
jitter;
telecommunication links;
data communication;
telecommunication equipment testing;
error statistics;
oscilloscopes;
data dependent jitter generation method;
jitter measurement methodology;
multiGbps serial IO;
serial communication links;
chip to chip application;
system-to-system application;
BER testing techniques;
deterministic jitter;
data dependent jitter injection filters;
continuous time interval analyzer;
real time sampling oscilloscopes;
90.
K longest paths per gate (KLPG) test generation for scan-based sequential circuits
机译:
用于基于扫描的时序电路的每门K条最长路径(KLPG)测试生成
作者:
Qiu W.
;
Jing Wang
;
Walker D.M.H.
;
Reddy D.
;
Xiang Lu
;
Zhuo Li
;
Weiping Shi
;
Balachandran H.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
sequential circuits;
fault diagnosis;
logic testing;
automatic test pattern generation;
boundary scan testing;
computational complexity;
built-in self test;
K longest paths per gate test generation;
delay faults;
test generation tools;
longest testable paths;
computational complexity;
scan based synchronous sequential circuits;
at-speed test methods;
ISCAS89 benchmark circuits;
industrial design;
transition faults testing;
logic testing;
built-in self test;
91.
Low overhead delay testing of ASICs
机译:
ASIC的低开销延迟测试
作者:
Gillis P.
;
McCauley K.
;
Woytowich F.
;
Ferko A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
application specific integrated circuits;
integrated circuit testing;
integrated circuit design;
fault diagnosis;
electronic engineering computing;
logic testing;
delay circuits;
automatic test pattern generation;
low overhead delay testing;
IBM ASIC;
chip geometries shrink;
cost effective delay test methodology;
burdened IC design;
transition fault coverage;
ASIC business;
design automation software;
stuck-at fault baseline;
random spot timing delay defects;
92.
Minimum testing requirements to screen temperature dependent defects
机译:
筛选温度相关缺陷的最低测试要求
作者:
Schuermyer C.
;
Ruffler J.
;
Daasch R.
;
Madge R.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated circuit testing;
crystal defects;
minimum testing requirements;
temperature defendent defects;
defect screening;
temperature dependent outliers;
multiple temperature testing;
die trace;
wafer sort;
0.18 micron;
30 degC;
85 degC;
93.
On-chip impulse response generation for analog and mixed-signal testing
机译:
片上脉冲响应生成,用于模拟和混合信号测试
作者:
Singh A.
;
Patel C.
;
Plusquellic J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
mixed analogue-digital integrated circuits;
analogue integrated circuits;
integrated circuit testing;
design for testability;
system-on-chip;
continuous time filters;
fault diagnosis;
regression analysis;
correlation methods;
onchip impulse response generation;
analog signal testing;
mixed-signal testing;
analog linear circuit components;
mixed-signal linear circuit components;
impulse response signatures;
DFT structure;
step responses;
pseudorandom patterns;
onchip cross-correlation methods;
autocorrelation methods;
statistical methods;
linear regression analysis;
defect screening;
continuous time filter;
active stable variable filter;
benchmark circuit;
device under test;
short resistive faults;
open resistive faults;
94.
On-chip mixed-signal test structures re-used for board test
机译:
片上混合信号测试结构重新用于电路板测试
作者:
Schuttert R.
;
van Geest D.C.L.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
boundary scan testing;
mass production;
design for testability;
mixed analogue-digital integrated circuits;
printed circuit testing;
integrated circuit interconnections;
IEEE standards;
on-chip mixed signal test structures;
analogue clusters;
mass production;
functional system tests;
boundary scan testing;
digital interconnections;
analogue interconnections;
IEEE Std 1149.4;
design for testability;
on-chip mixed signal blocks;
reduction board test;
95.
On-line testing field programmable analog array circuits
机译:
在线测试现场可编程模拟阵列电路
作者:
Haibo Wang
;
Kulkarni S.
;
Tragoudas S.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
field programmable analogue arrays;
integrated circuit testing;
analogue integrated circuits;
circuit stability;
active networks;
online testing;
FPAA circuit under test;
field programmable analog array circuits;
programmable resources;
flexible testing schedules;
circuit stability;
partitioned circuits;
circuit testability;
active networks;
96.
Performance characterization of mixed-signal circuits using a ternary signal representation
机译:
使用三态信号表示的混合信号电路的性能表征
作者:
Hak-Soo Yu
;
Shin H.
;
Chun J.H.
;
Abraham J.A.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
mixed analogue-digital integrated circuits;
signal representation;
integrated circuit testing;
analogue-digital conversion;
digital-analogue conversion;
built-in self test;
mixed signal circuit testing;
ternary signal representation;
signature characterization;
DUT;
device under test;
analog circuit testing;
lossy compression;
built-in circuits;
dynamic performance parameters;
SNR;
THD;
deltasigma DAC;
deltasigma ADC;
97.
Programmable at-speed array and functional BIST for embedded DRAM LSI
机译:
嵌入式DRAM LSI的可编程全速阵列和功能性BIST
作者:
Kume M.
;
Uehara K.
;
Itakura M.
;
Sawamoto H.
;
Kobayashi T.
;
Hasegawa M.
;
Hayashi H.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
DRAM chips;
built-in self test;
integrated circuit testing;
design for testability;
large scale integration;
cache storage;
programmable logic arrays;
logic testing;
SRAM chips;
functional BIST;
DFT;
design for test;
BIST engine;
embedded DRAM cache LSI;
SRAM macros;
programmable logic arrays;
98.
Realizing high test quality goals with smart test resource usage
机译:
通过智能测试资源的使用实现高测试质量目标
作者:
Xinli Gu
;
Wang C.
;
Lee A.
;
Eklow B.
;
Kun-Han Tsai
;
Tofte J.A.
;
Kassab M.
;
Rajski J.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
design for testability;
automatic test pattern generation;
built-in self test;
logic testing;
fault diagnosis;
integrated circuit testing;
application specific integrated circuits;
smart test resource usage;
high test quality;
ASIC design sizes;
advanced deep submicron technology;
fault models;
test vectors;
cost constraints;
test quality metrics;
industrial designs;
DFT techniques;
ATPG;
compressed deterministic patterns;
logic BIST;
pseudorandom patterns;
stuck at tests;
embedded deterministic test;
99.
Risks associated with faults within test pattern compactors and their implications on testing
机译:
与测试模式压实器内的故障相关的风险及其对测试的影响
作者:
Metra C.
;
Mak T.M.
;
Omana M.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
integrated circuit testing;
design for testability;
risk analysis;
risk analysis;
test pattern compactors;
DFT structures;
compactors internal faults;
product quality;
fault secure property;
faulty products;
100.
Test strategy cost model innovations
机译:
测试策略成本模型创新
作者:
Michel C.
;
Reinosa R.D.
会议名称:
《Test Conference, 2004. Proceedings. ITC 2004》
|
2004年
关键词:
production testing;
inspection;
investment;
manufacturing processes;
printed circuit testing;
costing;
test strategy cost model;
cost model innovations;
inspection techniques;
manufacturing process;
trade off analysis;
return on investment analysis;
manufacturing test strategy;
National Electronics Manufacturing Initiative;
product test strategies;
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