A 10 Gb/s ATM data synchronizer

摘要

Asynchronous transfer mode (ATM) data comes from different sources, and it is by nature bursty, hence causing the incoming phase and exact bit rate to vary from burst to burst. In order to retime the bursty data, a conventional yet low-Q clock recovery scheme could be used, but the downstream system components would have to cope with the consequent clock interruptions and variations in phase and frequency. This work presents a phase agile data synchronizer integrated circuit that retimes bursty ATM cells at 10 Gb/s to an external 10 GHz clock. The integrated circuit comprises an analog variable data delay, a phase detector, an edge detector, a loop filter, and a data retime. It has a total delay range of 200 pS. The integrated circuit has been fabricated in both AlGaAs/GaAs and InGaP/GaAs HBT technology.