A low-power 128/spl times/1-bit GaAs FIFO for ATM packet switcher

摘要

A low-power 128/spl times/1-b GaAs first-in first-out (FIFO) IC using two-phase dynamic FET logic (TDFL) for high-speed ATM switcher has been successfully demonstrated. In order to overcome the difficulty of low power consumption for the ATM switcher using CMOS FIFO while keeping high-speed operation, a higher speed GaAs FIFO using a low-power circuit technique is designed. The ATM switch architecture, when optimized for use with those higher speed FIFO's, can benefit from reduced power and wiring complexity. The advantage of self-latching property as well as its low power dissipation and compact layout of TDFL gates is used in the FIFO. The FIFO, which contains 270 TDFL gates and 1930 static gates, is shown to operate at 200 MHz with power dissipation of 100 mW. The measured maximum and minimum operating frequencies are 420 and 100 MHz, respectively. The possibility of 10/spl times/ smaller power dissipation, and 4/spl times/ smaller system configuration of the ATM switcher using the GaAs FIFO compared with the CMOS case is expected.