A 40-Gb/s integrated clock and data recovery circuit in a 50-GHz f/sub T/ silicon bipolar technology

摘要

Clock and data recovery (CDR) circuits are key electronic components in future optical broadband communication systems. In this paper, we present a 40-Gb/s integrated CDR circuit applying a phase-locked loop technique. The IC has been fabricated in a 50-GHz f/sub T/ self-aligned double-polysilicon bipolar technology using only production-like process steps. The achieved data rate is a record value for silicon and comparable with the best results for this type of circuit realized in SiGe and III-V technologies.