A 10-bit 200-MS/s CMOS parallel pipeline A/D converter

摘要

This paper describes a 10-bit 200-MS/s CMOS parallel pipelinenanalog-to-digital (A/D) converter that can sample input frequenciesnabove 200 MHz. The converter utilizes a front-end sample-and-hold (S/H)ncircuit and four parallel interleaved pipeline component A/D convertersnfollowed by a digital offset compensation. By optimizing for power innthe architectural level, incorporating extensively parallelism andndouble-sampling both in the S/H circuit and the component ADCs, a powerndissipation of only 280 mW from a 3.0-V supply is achieved. Implementednin a 0.5-Μm CMOS process, the circuit occupies an area of 7.4nmm2. The converter achieves a differential nonlinearity andnintegral nonlinearity of ±0.8 LSB and ±0.9 LSB,nrespectively, while the peak spurious-free-dynamic-range is 55 dB andnthe total harmonic distortion better than 46 dB at a sampling rate ofn200 MS/s