Measurements and analysis of PLL jitter caused by digital switchingnoise

摘要

When integrating analog and digital circuits onto a mixed-modenchip, power supply noise coupling is a major limitation on thenperformance of the analog circuitry. Several techniques exist fornreducing the noise coupling, of which one of the cheapest is separatingnthe power supply distribution networks for the analog and digitalncircuits. Noise coupling from a digital noise-generating circuit throughnthe power supply/substrate into an analog phase-locked loop (PLL) isnanalyzed for three different power supply schemes. The main mechanismsnfor noise coupling are identified by comparing different PLLs andnvarying their bandwidths. It is found that the main cause of jitternstrongly depends on the power supply configuration of the PLL.nMeasurements were done on mixed-mode designs in a standard 0.25-Μmndigital CMOS process with a low-resistivity substrate. The same circuitsnwere also implemented with triple-well processing for comparisons