An 8-bit 10 MS/s folding and interpolating ADC using thecontinuous-time auto-zero technique

摘要

An 8-bit 10-MS/s folding and interpolating analog-to-digitalnconverter (ADC) using the continuous-time auto-zero technique isnpresented. Compared with the conventional architecture, it can improventhe nonlinear errors and enhance the signal-to-noise-and-distortionnratio (SNDR). Both architectures have been fabricated on the same die ofna 0.35-Μm DPDM CMOS process and measured under the same conditionsnwith a 2.7-V supply voltage and 10-MHz sampling rate. Thencontinuous-time auto-zero architecture shows an ENOB of 7.7 bits whilenthe conventional one shows 5.8 bits