Design methodology of embedded DRAM with virtual-socketarchitecture

摘要

This paper proposes the virtual-socket architecture in order tonreduce the design turn-around time (TAT) of the embedded DRAM. Thenrequired memory density and the function of the embedded DRAM are systemndependent. In the conventional design, the DRAM control circuitry withnthe DRAM memory array is handled as a hardware macro, resulting in thenincrease in design TAT. On the other hand, our proposed architecturenprovides the DRAM control circuitry as a software macro to takenadvantage of the automated tools based on synchronous circuit design.nWith array-generator technology, this architecture can achieve highnquality and quick turn-around time (QTAT) of flexible embedded DRAM thatnis almost the same as the CMOS ASIC. We applied this virtual-socketnarchitecture to the development of the 61-Mb synchronous DRAM core usingn0.18-Μm design rule and confirmed the high-speed operation, 166 MHznat CAS latency of two, and 180 MHz at that of three. The experimentalnresults show that our proposed architecture can be applied to thendevelopment of the high-performance embedded DRAM with design QTAT