A programmable focal-plane MIMD image processor chip

摘要

An 80×78 pixels vision chip for focal-plane image processingnis presented. The chip employs a Multiple-Instruction-Multiple-Datan(MIMD) architecture to provide five spatially processed images innparallel. The size, configuration, and coefficients of the spatialnkernels are programmable. The chip's architecture allows thenphotoreceptor cells to be small and parked densely by performing allncomputations on the read-out, away from the array. The processing corenuses digitally programmed current-mode analog computation. Operating atn9.6 K frames/s in 800-lux ambient light, the chip consumes 4 mW from an2.5-V power supply. Performing 11×11 spatial convolutions, annequivalent computation (5.5 bit scale-accumulate) rate of 12.4 GOPS/mWnis achieved using 22 mm2 in a 1.2-Μm CMOS process. Thenapplication of the chip to line-segment orientation detection is alsonpresented