An on-chip ESD protection circuit with low trigger voltage inBiCMOS technology

摘要

A novel low-trigger dual-direction on-chip electrostatic dischargen(ESD) protection circuit is designed to protect integrated circuitsn(ICs) against ESD surges in two opposite directions. The compact ESDnprotection circuit features low triggering voltage (~7.5 V), shortnresponse time (0.18-0.4 ns), symmetric deep-snap-back I-Vncharacteristics, and low on-resistance (~Ω). It passed the 14-kVnhuman body model (HBM) ESD test and is very area efficient (~80 V/Μmnwidth). The new ESD protection design is particularly suitable fornlow-voltage or multiple-power-supply IC chips