A low-power multi-bit /spl Sigma//spl Delta/ modulator in 90-nm digital CMOS without DEM

摘要

Multi-bit sigma-delta modulators are widely used in analog-to-digital conversion especially in the modern deep-submicron CMOS process. As the quantizer resolution of /spl Sigma//spl Delta/ modulators increases, the SNR performance improves. However, the feedback DAC has to maintain high linearity. The general practice to achieve that is to use dynamic element matching (DEM). The methodology proposed in this paper will greatly reduce the complexity or even avoid usage of DEM for multi-bit /spl Sigma//spl Delta/ modulators. The proposed methodology-truncation error shaping and cancellation-reduces the feedback DAC levels for multi-bit quantizers. A prototype was designed in a standard CMOS 90-nm process to demonstrate the proposed methodologies. It achieved targeted performance without DEM at low power consumption with small silicon area.