A 12.5-Mb/s to 2.7-Gb/s Continuous-Rate CDR With Automatic Frequency Acquisition and Data-Rate Readback

摘要

A continuous-rate clock and data recovery (CDR) circuit that operates from 12.5 Mb/s to 2.7 Gb/s is described. The circuit automatically detects a change in input data rate, acquires the new frequency, and reports the data rate to the user without the need for an external reference clock or any programming. At 2.5 Gb/s, it achieves an acquisition time of 1 ms. In tracking mode, it uses a dual DLL/PLL to provide superior jitter performance compared to a standard second-order loop. At the OC48 data rate, it achieves a jitter transfer bandwidth of 500 kHz and a jitter tolerance bandwidth of 3 MHz. It is on a 0.35-μm double-poly, triple-metal (DPTM) BiCMOS process, dissipates 235 mA from a 3.3-V supply, and occupies 9 mm{sup}2. It is in a compact 5×5 mm{sup}2 LFCSP package.