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首页> 外文期刊>IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control >Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays
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Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays

机译:使用2D CMUT阵列进行3D声学成像的前端集成电路的设计

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Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMUT element, we developed an electrical CMUT model with parameters derived through finite element analysis, and performed both the pre- and postlayout verification. An experimental chip consisting of 4 /spl times/ 4 array of the designed circuit cells, each cell occupying a 200 /spl times/ 200 /spl mu/m/sup 2/ area, was formed for the initial test studies and scheduled for fabrication in 0.8 /spl mu/m, 50 V CMOS technology. The designed circuit is suitable for integration with CMUT arrays through flip-chip bonding and the CMUT-on-CMOS process.
机译:前端电子设备与2D电容式微机械超声换能器(CMUT)阵列的集成由于元件尺寸小和通道数大而成为一个具有挑战性的问题。我们介绍了使用2D CMUT阵列进行3D超声成像的前端驱动读出集成电路的设计和验证。专用于单个CMUT阵列元件的电路单元由高压脉冲发生器和低噪声读出放大器组成。为了与CMUT元素一起分析电路单元,我们开发了具有通过有限元分析得出的参数的电CMUT模型,并执行了布局前和布局后验证。形成了由4个/ spl次/ 4个设计电路单元阵列组成的实验芯片,每个单元占据200 / spl次/ 200个/ spl mu / m / sup 2 /面积,用于初始测试研究并计划制造采用0.8 / spl mu / m,50 V CMOS技术。该设计电路适合通过倒装芯片键合和CMUT-on-CMOS工艺与CMUT阵列集成。

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