We present a new design and test solution for built-in self-test (BIST), supporting on-line and off-line testing techniques, sharing hardware resources. For off-line testing, a standard signature analysis method is applied, with its high fault coverage, low hardware overhead, and seamless integration in a scan-based architecture. For on-line testing, a good fault coverage is achieved by employing appropriate cyclic codes. The hardware for the BIST implements the two modes with very low overhead compared to existing techniques by sharing physical resources. The sharing is achieved by exploiting the concatenation features of linear feedback shift register or linear cellular automata registers. The method is applicable to general circuitry. A template for this new design and test technique is presented, together with case studies.
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