On the nature and inadequacies of transport timing delay constructs in VHDL descriptions

摘要

The ability to accurately represent and execute the timing behavior of digital hardware constitutes a fundamental characteristic of any hardware description language including ADLIB-SABLE and the US DoD's VHDL. Unlike its predecessor hardware description languages that utilized a single delay construct, the VHDL grammar proposes two syntactic constructs-inertial and transport delays, and the VHDL language defines their semantics to facilitate accurate modeling of the timing behavior. Inertial delays are utilized to model the timing behavior of digital components such as gates and flip-flops where a new input signal must persist for a minimum specified duration so as to initiate a change in the state of the component. Transport delays, on the other hand, are designed to model devices with infinite frequency response, i.e., where any new input signal, regardless of its duration, will initiate a change in the state of the component. Examples of such devices include bus and clock interconnect lines. The design of transport delay suffers from two major flaws. First, there is an implicit assumption that in an interconnect with multiple taps, only one tap is a driver, and the signal reaches the other taps delayed only by the time necessary for the electromagnetic propagation. Thus, the perturbation due to reflection at the intermediate taps is ignored, and this results in incorrect timing behavior. Second, for today's increasing higher clock speeds and newer bus design techniques such as Intel's PCI, the corresponding clock time period increasingly compares with the delay along the interconnects. Thus, interconnects increasingly behave like transmission lines, and accurate modeling warrants the use of transmission line analysis. This paper proposes new additions to the existing VHDL grammar, and defines new semantics in the language to accurately model the timing behavior of high-frequency buses and clock lines with multiple, distinct taps. The proposed language constructs utilize transmission-line analysis to model the timing behavior of "long" lines. A long line is characterized by the inequality {t/sub r//T/sub prop//spl les/2}, where t/sub r/ and T/sub prop/ represent the finite signal transition time for the wave and the propagation delay of the wave from the driver to the load, respectively. True transmission line analysis, however, requires analog simulation that is accurate, yet painfully slow. Also, analog simulation is incompatible with the event-driven simulation algorithm that constitutes the basis of execution of hardware description languages. This paper develops an algorithm that is based on the underlying transmission-line analysis, but is event driven and computationally fast. It computes the state of incident, reflected, and refracted (or transmitted) waves at each of the distinct, discrete taps along the bus, thereby generating accurate timing behavior. This paper also presents the design of a simulator that implements the proposed timing construct. A number of experiments are conducted wherein an Ethernet bus, under "collision" and "no-collision" scenarios, a TTL wired-OR bus under single driver and wired-OR glitch scenarios, and the new Intel PCI bus are modeled and executed on the simulator. Performance analysis reveals that while the simulation results accurately match the actual behavior of buses, the simulation executes fast.