A Study of Phase Noise and Frequency Error of a Fractional-N PLL in the Course of FMCW Chirp Generation

摘要

This paper presents the theoretical and experimental results on the phase noise spectrum and the rms frequency error of a fractional-N phase-locked loop (PLL) under frequency-modulated continuous-wave (FMCW) chirp generation. The phase noise spectrum under modulation is analytically calculated for a second-order charge pump PLL with a feedback divider ratio linearly changing over time. This is followed by an analysis of the steady-state rms frequency error of the output frequency after PLL settling is achieved during chirp generation. A fractional-N PLL with integrated frequency ramp generator is presented. Phase noise and jitter measurements on the PLL under modulation are performed at the output of the programmable feedback divider. The resulting low-frequency rms jitter is reduced by about 9 dB with doubling the charge pump current, and reduced by about 6 dB with halving the ramp slope. The rms frequency error under FMCW modulation is measured at the modulated voltage-controlled oscillator output. The dependence of the frequency error on the loop filter capacitance for various ramp slopes is given. A frequency error of 112 kHz is achieved with a ramp slope of 1.28 GHz/80 mu s at a carrier frequency of 62 GHz. The noise measurements are in good agreement with the developed phase noise model. A programmable loop filter capacitance is suggested to accommodate the static phase offset and the resulting noise performance to the ramp slope.