FPGAs to ASIC: Prototype to Production

摘要

Many engineers buy into the conventional wisdom of designing with an FPGA and converting to an ASIC when higher volume or better performance is needed. The problem with this thinking is that FPGAs are standard products with a fixed set of constraints and requirements, as well as neat features and optional extras that are incrementally free. Converting your FPGA design to an ASIC with a different set of constraints and costs is inefficient because many of the "free" choices in the FPGA domain have a dollar or performance cost in the ASIC. Conversely, you are forced to ignore features available only in the ASIC because of your focus on taking the FPGA through die entire design cycle, limiting your design freedom and increasing costs.