A rapid prototyping architecture and methodology for logic emulation of large ASICs using multiple FPGAs.

摘要

Recent advances in integrated circuit (IC) technology have contributed to the practical design of up to ten million gates on a single digital application specific integrated circuit (ASIC). Despite this extraordinary capacity, design and verification tools and methods have lagged. Designers are attempting to deal with the issues via large scale design reuse: for example, microprocessor cores. In this system-on-a-chip (SoC) era, design verification through event based simulation (EBS) is not attractive due to the poor performance that leads to a sign-off with an insufficient number of vectors. Designers need orders of magnitude performance improvement in functional design verification.; Logic emulation through multiple field programmable gate arrays (FPGAs) is an interesting technique that has been employed with mixed review over the last several years. It provides approximately one million times the verification performance over EBS of the structural description. However, it is plagued with several problems, including cost, ease of use, the need for a plug-in, and the need for a separate source description for emulation.; It can be shown that the quality of the circuit partition dramatically affects the viability of logic emulation in this form to provide a cost-effective result. The particular figure of merit that governs is the relationship between the number of inputs and outputs demanded by a subcircuit of given capacity. This relationship is given by the Rent exponent. If the mean Rent exponent can be maintained low throughout the hierarchy of a design, then its mapping to multiple FPGAs can yield a cost-effective result.; This dissertation demonstrates such a result through the development of a methodology and architecture that employs multiple FPGAs. To arrive at that architecture, fifteen new designs, including ten that are original work, were completed using modern design reuse methodology. A detailed analysis of the circuit topologies shows that they can be partitioned according to rules for partitioning for verification, a manual technique today that can be made automatic, and thereby made to exhibit small Rent exponent throughout the hierarchy.; Further, although the motivation for it is to speed the verification, it is demonstrated that the inclusion of test benches and instrumentation in the programmable logic further reduces the Rent exponent of the design.; The observations above lead to a simplification in the architecture for employment of multiple FPGAs that leads to a dramatically faster and less expensive design verification device.