Low‐power heterogeneous uncore architecture for future 3D chip‐multiprocessors

摘要

Uncore components such as on‐chip memory systems and on‐chip interconnects consume a large amount of energy in emerging embedded applications. Few studies have focused on next‐generation analytical models for future chip‐multiprocessors ( CMP s) that simultaneously consider the impacts of the power consumption of core and uncore components. In this paper, we propose a convex‐optimization approach to design heterogeneous uncore architectures for embedded CMP s. Our convex approach optimizes the number and placement of memory banks with different technologies on the memory layer. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias as a viable solution in building three‐dimensional (3D) CMP s is another important target of the proposed approach. Experimental results show that the proposed method outperforms 3D CMP designs with hybrid and traditional memory architectures in terms of both energy delay products ( EDP s) and performance parameters. The proposed method improves the EDP s by an average of about 43% compared with SRAM design. In addition, it improves the throughput by about 7% compared with dynamic RAM ( DRAM ) design.