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In Situ SiO2 Passivation of Epitaxial (100)and (110)InGaAs by Exploiting TaSiOx Atomic Layer Deposition Process

机译:外延原位SiO2钝化(100)利用TaSiOx原子层沉积工艺制备和(110)InGaAs

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摘要

In this work, an in situ SiO2 passivation technique using atomic layer deposition (ALD) during the growth of gate dielectric TaSiOx on solid-source molecular beam epitaxy grown (100)InxGa1–xAs and (110)InxGa1–xAs on InP substrates is reported. X-ray reciprocal space mapping demonstrated quasi-lattice matched InxGa1–xAs epitaxy on crystallographically oriented InP substrates. Cross-sectional transmission electron microscopy revealed sharp heterointerfaces between ALD TaSiOx and (100) and (110)InxGa1–xAs epilayers, wherein the presence of a consistent growth of an ∼0.8 nm intentionally formed SiO2 interfacial passivating layer (IPL) is also observed on each of (100) and (110)InxGa1–xAs. X-ray photoelectron spectroscopy (XPS) revealed the incorporation of SiO2 in the composite TaSiOx, and valence band offset (ΔEV) values for TaSiOx relative to (100) and (110)InxGa1–xAs orientations of 2.52 ± 0.05 and 2.65 ± 0.05 eV, respectively, were extracted. The conduction band offset (ΔEC) was calculated to be 1.3 ± 0.1 eV for (100)InxGa1–xAs and 1.43 ± 0.1 eV for (110)InxGa1–xAs, using TaSiOx band gap values of 4.60 and4.82 eV, respectively, determined from the fitted O 1s XPS loss spectra,and the literature-reported composition-dependent InxGa1–xAs band gap. The insitu passivation of InxGa1–xAs using SiO2 IPL during ALD of TaSiOx and the relatively large ΔEV and ΔEC valuesreported in this work are expected to aid in the future developmentof thermodynamically stable high-κ gate dielectrics on InxGa1–xAswith reduced gate leakage, particularly under low-power device operation.
机译:在这项工作中,报道了在InP衬底上生长的(100)InxGa1-xAs和(110)InxGa1-xAs固体源分子束外延生长栅极电介质TaSiOx的过程中,采用原子层沉积(ALD)的原位SiO2钝化技术。 X射线相互空间映射显示了在晶体学取向的InP衬底上准晶格匹配的InxGa1-xAs外延。横截面透射电子显微镜显示在ALD TaSiOx与(100)和(110)InxGa1-xAs外延层之间存在尖锐的异质界面,其中还观察到约0.8 nm的故意形成的SiO2界面钝化层(IPL)持续生长。 (100)和(110)InxGa1-xAs中的每一个。 X射线光电子能谱(XPS)显示SiO2掺入复合TaSiOx中,并且TaSiO x 的价带偏移(ΔE V )值相对于(100)和(110)In x Ga 1– x As的取向分别为2.52±0.05和2.65±0.05 eV。对于(100)In x E C )为1.3±0.1 eV >(110)In x Ga 1的> Ga 1– x As和1.43±0.1 eV – x As,使用TaSiO x 带隙值为4.60和根据拟合的O 1s XPS损耗谱确定的分别为4.82 eV,以及文献报道的依赖成分的In x Ga 1– x As带隙。在In x Ga 1– x As的SiO 2 IPL原位钝化TaSiO x 和相对较大的Δ E V 和Δ E < sub> C 值在这项工作中报告的数据有望对未来的发展有所帮助In x Ga 1– x As上热力学稳定的高κ栅极电介质的特性降低了栅极泄漏,特别是在低功耗设备操作下。

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