带降场层部分衬底SOI高压器件模型

摘要

In order to obtain good compromise of the breakdown voltage and specific on-resistance of SOI-LDMOS,a SOl high voltage device with reduced-field layer and partial substrate is proposed.The breakdown voltage is improved greatly due to no limit to the vertical voltage by etching the substrate below the drift region and drain side,and the reduced-field layer is leaded into drift region to improve the specific on-resistance effectively.The breakdown voltage and specific on-resistance of the new structure are researched by simulating with 2-D MEDICI.The simulation results show the breakdown voltage is enhanced significantly by maintaining the low on-resistance.%为了获得SOI-LDMOS器件耐压和比导通电阻的良好折中,提出了一种带降场层部分衬底SOI高压器件的新结构.通过蚀刻掉常规SOI-LDMOS漂移区和漏端下方的衬底,使器件击穿电压不再受纵向限制.同时在漂移区引入了降场层,从而有效地改善了比导通电阻.基于二维仿真软件对该器件的耐压和比导通电阻特性进行了研究,结果表明该器件在不增加比导通电阻的情况下,人大提高了耐压能力.