基于FPGA的异步FIFO的研究和设计

摘要

A practical design technique is proposed, through the analysis of the structure and operational principle of asynchronous FIFO, for meeting the difficult point of asynchronous FIFO. Ensuring writing in or reading out data without error by way of controlling full and empty signal. Using the method of gray mode reduces the incidence of metastable state maximum. The result shows that the design can make data write in or read out steady and have a high resource utilization rate.%针对设计异步FIFO的难点,分析了异步FIFO的结构和工作原理,提出了一种切实可行的设计方法.通过对空满信号的控制确保数据的正确写入与读出,采用了格雷码的方式最大限度降低了电路中亚稳态出现的概率.结果表明,该设计能够使数据稳定地写入和读出,同时资源利用率较高.