高精度ADC转换核的设计

摘要

在DSP的A/D转换电路中,转换核电路是整个电路的核心模块,包括时钟电路、采样保持电路（S/H）、MDAC电路、比较器电路、子ADC译码电路、冗余位数字校正电路等。同时转换核电路通常又是整个A/D电路中功耗最大的模块,其性能直接决定了整个A/D转换器的性能。文章介绍了一种l2位25MS/s转换核电路设计。该电路采用TSMC标准数字0.18μm CMOS工艺进行设计,版图面积为1.69mm2。采用Hspice对整个电路进行仿真。仿真的结果表明,电路工作于25MS/s、输入信号频率为6.5MHz时,输出信号的SFDR为75dB、SNDR为60dB,而整个电路的功耗为33.41mW。该设计为高精度DSP的设计提供了良好的技术基础。%The conversion core circuit is the hard core in A/D of DSP.It include： CLK,S/H,MDAC,et al.Conversion core circuit also is the largest power consumer in ADC,usually.Its character determines the entire ADC.This paper introduces a 12bit 25MS/s conversion core circuit design.This circuit use 0.18μm CMOS technology,and layout is 1.69mm2.Hspice is used for simulating.The results show that： SFDR is 75dB,SNDR is 60dB,and power is 33.41mW,when the circuit works on 25MS/s,and input signal frequency is 6.5MHz.This work supplies a good technologic base for high precision DSP design.