适用于多核处理器的簇状片上网络设计

摘要

This paper presents a novel clustered Network-on-Chip(NoC) architecture for multi-core processor. The proposed architecture is a cluster array organized as a two-dimensional mesh. Each cluster includes three processors, one Direct Memory Access(DMA) and one cluster shared memory. The multi-core processor using such NoC architecture can obtain high communication efficiency and memory utilization ratio. It design a four-cluster prototype system and implement the 3 780-point Fast Fourier Transform(FFT) on it. In FFT application, the memory utilization ratio increases to 79.5%.%提出一种新型簇状片上网络架构.该架构以二维网状拓扑结构连接各个簇单元,每个簇单元由3个处理器、1个直接访存单元和1个簇共享存储单元组成.基于该架构的多核处理器可以获得更高的通信效率及存储器利用率.在实验系统上实现3 780点的快速傅里叶变换,结果表明,在快速傅里叶变换应用中存储器的利用率能提升至79.5％.