PCI Express是当前广泛应用的高速串行传输标准,其V1.0版本提供2.5Gbps的高速传输带宽.对于高速串行传输而言,精确的发送定时与接收同步是其关键技术.本文在详细分析PCI Express物理层技术的基础上,特别针对串行接收端的数据时钟恢复CDR技术展开研究,采用基于锁相环结构的数据时钟恢复技术设计了一款2.5Gbps速率的高速物理层电路,并基于0.13μm CMOS工艺设计了版图实现.基于HSPICE的模拟结果表明,此设计完全满足了PCI Express的要求,其抖动的均方根值为1.51ps,峰峰值为8.14ps.%PCI-express is a new generation of high-speed serial link in which the bandwidth is 2. 5Gbps for version 1. 0. The most important portion is SerDes. In this article,we focused at the clock date recovery technology, and performed a 2. 5Gbps high-speed physical macro for PCI-Express v1.0 with 0. 13 μm CMOS process, the jitter(RMS) is 1. 51ps,and jitter (peak-to peak) is 8.14ps.
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