可重构分组密码协处理器二维指令架构

摘要

为能够进一步提升可重构分组密码协处理器的指令并行度和密码处理能力,以优化可重构分组密码协处理器的性能、面积、功耗比为目的,分别分析指令调度与密码运算之间的关系和特征,提出可重构分组密码协处理器二维指令架构,该架构能够增加指令执行周期,提高可重构功能单元的利用率.通过3种分组密码算法进行实现,结果表明,改进后的可重构分组密码协处理器的指令并行度是改进前的2-4倍.%To improve the instruction parallelism of reconfigurable block cipher co-processor (RBCCP),the operation characteristic of the block cipher and the operating instruction set of RBCCP were analyzed.The 2D instruction set architecture was proposed and the method of instruction executing and the parallel processing of 2D instruction setwere researched,and a processor architecture for the 2D instruction set was designed.Results of realizing of 3 block ciphers show that the parallelism level of 2D instruction set architecture of RBCCP is 2-4 times higher than that of the original one.