一种优化的AES算法及其FPGA实现

摘要

For the encryption and decryption structure of AES is not consistent,an optimized AES algorithm with a unified encryption and decryption process is proposed in this paper.Using the fully pipelined architecture, the proposed circuit achieves an effective tradeoff between speed and resources, among which the S-box and inverse S-box are implemented applying the finite field algorithm based on regular basis.With the analysis of the path delay of each module, the AES round transformation is divided into 6 stages.Results implemented in the Xilinx`s XC7VX485T FPGA show that the hardware resource consumption is 19006LUTs,the maximum frequency is 724.323MHz and the throughput can get to 92.713Gbps, thus obtaining a very good acceleration effect.%针对AES算法加密解密结构的不一致提出了一种优化算法,得到了统一的加密解密流程,有效节省了资源消耗.为取得速度和资源的折中,AES加密解密主体采用内外混合流水线结构,其中S-box和逆S-box采用基于正规基的有限域算法实现.基于对各电路模块路径延时的分析,对AES轮变换进行了6级流水线划分.在Xilinx公司XC7VX485T FPGA上综合结果显示:电路资源消耗为19006LUTs,最高工作频率为724.323MHz,数据吞吐量为92.713Gbps,获得了非常好的加速效果且有效降低了资源消耗.